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Meta · 2 weeks ago

ASIC Engineer, Networking Architecture and Modeling

Sunnyvale, CA

Full-time

Onsite

Senior Level

$146K/yr - $209K/yr

6+ years exp

Meta builds technologies that help people connect and grow businesses. As a Networking ASIC Engineer on the Infrastructure Silicon team, you will shape networking architecture for AI training and inference accelerators and develop high-fidelity C++ models to enable early software development and performance analysis.

Computer Software

Comp. & Benefits

Responsibilities

Collaborate with architecture engineers to define specifications for one or more subsystems of an integrated or discrete NIC ASIC

Develop and maintain C++ models of networking subsystems—including QEMU, NIC, RoCE, and UAL models—for architecture exploration, performance analysis, and software development

Provide technical support in functional model development to enable networking firmware creation

Support networking model development, performance analysis, and correlation with design implementation

Work with software and firmware teams to ensure C++ models are aligned with system requirements and enable early software bring-up

Provide expected key performance indicators for performance analysis of the subsystems

Qualification

C++ modelingNetworking ASIC developmentQEMUPerformance analysisData center networkingPCIe-based NICsTechnical supportCollaboration

Required

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

6+ years of experience working in networking ASIC development targeted for enterprise, data-center, or hyperscaler use cases

Hands-on experience developing and maintaining C++ models for NIC, RoCE, UAL or similar networking architectures

Experience with QEMU or similar simulation frameworks for hardware modeling

Preferred

Experience working with large clusters of Ethernet or RoCEv2 or Infiniband or NVlink fabrics

Knowledge of ASIC development on advanced process nodes using chiplet-based solutions

Experience and knowledge of data center networking solutions used in large-scale clusters, including shallow buffered switches, TOR switches, routers, GPU and CPU servers/acceleration devices

Experience in using performance models, performance analysis, and performance correlation

Experience in developing PCIe-based NICs, Front-end and Back-end NICs

Experience with QEMU NIC modeling, UAL modeling, and RoCE modeling using C++

Experience integrating C++ models with system simulation environments (e.g., QEMU, SystemC, or custom frameworks)