Acceler8 Talent ยท 2 weeks ago
RTL Design Engineer
Acceler8 Talent is an early-stage startup building a compute platform for AGI, and they are seeking an experienced RTL Engineer. The role involves owning the top-level RTL integration flow of large, complex SoCs, collaborating with various teams to ensure a seamless, production-ready product.
Responsibilities
Own the top-level RTL integration of large, complex SoCs from subsystem drop to sign-off
Develop and maintain integration methodologies for scalable assembly across full-chip builds
Drive chip-level reviews of connectivity, functionality, timing, and PPA closure across milestones (integration freeze, design freeze, tapeout)
Work closely with subsystem owners, verification, DFT, and physical design teams to resolve integration issues and ensure clean handoff to downstream flows
Debug and resolve top-level RTL issues (connectivity mismatches, CDC/RDC, resets, clocks, design lint) across the chip hierarchy
Deliver sign-off quality RTL suitable for synthesis, equivalence checking, and emulation
Qualification
Required
Hands-on experience with top-level RTL integration of ASICs or SoCs, from subsystem assembly through production silicon
Strong skills in SystemVerilog for integration and debugging; familiarity with Python, C/C++, or scripting languages to support integration flows
Deep knowledge of chip-level design concepts: clocks, resets, power domains, CDC/RDC, lint, connectivity, and hierarchical build flows
Experience with synthesis and sign-off flows (equivalence checking, lint, DFT/scan stitching, power/timing checks)
Proven track record of working across multi-disciplinary teams (design, verification, physical design, DFT) to achieve high-quality tapeouts
Preferred
familiarity with emulation platforms and methodologies
experience with silicon bring-up and debug