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Acceler8 Talent · 3 weeks ago

Senior Design Verification Engineer

San Francisco Bay Area

Full-time

Hybrid

Senior Level

$200K/yr - $230K/yr

5+ years exp

Acceler8 Talent is looking for a driven and energetic Design Verification Engineer to join an early-stage start-up developing foundational technology to support the next generation of AI systems. This role offers the opportunity to take ownership of verifying key components of an AI inference chiplet designed to support models ranging from very small to extremely large.

Staffing & Recruiting

Hiring Manager

Mia Macdonald

Responsibilities

Owning verification planning and execution at both fabric-level and full-chip scope, ensuring thorough validation across multiple design layers

Working closely with architecture, firmware, and design teams to translate specifications into detailed and effective verification plans

Developing sophisticated verification environments, including constrained-random stimulus, checkers, scoreboards, and assertions to validate functionality and coverage

Defining and executing end-to-end verification strategies, including coverage analysis, regression automation, and data-driven optimization of verification quality

Promoting strong verification practices through code reviews, sprint-based execution, and structured feature rollout

Exploring and adopting new verification methodologies, automated workflows, and emerging tools, including AI-assisted verification techniques

Qualification

SystemVerilog/VerilogUVMC/C++Verification LeadershipFabric-level verificationFull-chip verificationTest planningDebuggingEmbedded software developmentAI-assisted verification

Required

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field

5-10+ years of hands-on verification experience, including test planning, environment development, test creation, and debugging across IP, SoC, and system-level designs

Deep experience with fabric-level and full-chip verification approaches and best practices

Strong proficiency in SystemVerilog/Verilog, UVM, and C/C++, including embedded software development and validation for RISC-based processors

Proven ability to build scalable verification infrastructures, apply coverage-driven verification, and implement assertion-based verification methodologies