NVIDIA · 3 weeks ago
Senior Custom Circuits Timing Engineer
US, CA, Santa Clara
Full-time
Hybrid
Senior Level
$168K/yr - $264K/yr
6+ years expNVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. They are seeking a motivated Senior Timing Closure Engineer to join their dynamic and growing Circuit Solutions Group, focusing on improving netlist and timing quality while solving complex technical challenges through collaboration.
AI InfrastructureArtificial Intelligence (AI)Consumer ElectronicsFoundational AIGPUHardwareSoftwareVirtual Reality
Responsibilities
Participate in groundbreaking processor design in deep submicron technologies
Work as part of a global circuits team alongside custom circuit designers to drive timing analysis and closure of custom circuit macros (digital, semi-custom and mixed-signal analog)
Apply knowledge and experience to standardize and improve timing convergence flows working with methodology teams
Develop timing models and methodology for innovative and unique custom macro designs at transistor level
Develop timing models and methodology for standard cell and mixed-signal custom macro designs
Validate timing of custom circuit designs using NanoTime and various SPICE simulations to ensure proper timing of innovative circuit topologies
Work with circuit designers, tool developers, and methodology teams to validate transistor level timing accuracy and correctness
Work with PD, DFX, Clocks, and other teams on timing closure strategy, timing constraints, timing and power convergence, DFT, as well as ECO implementation
Qualification
Required
BS (or equivalent experience) in Electrical or Computer Engineering
6+ years of experience for Masters and 8+ years for Bachelors with majority of experience in custom circuit timing analysis/closure
Expertise and in depth knowledge of industry standard transistor level STA tools such as NanoTime and timing convergence tools
Solid experience in timing constraints generation & management, and timing analysis/closure with mixed-signal designs
Basic level understanding of transistor-level circuits and SPICE simulations for correlation to static timing and noise results
Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
Knowledge in process variation effect modeling and experience in design convergence taking into account process variations
Familiarity with clocking specs such as jitter, IR drop, crosstalk, etc
Solid understanding of timing models and the usage of .libs in NanoTime as well as PrimeTime
Great teammate with outstanding interpersonal skills
Preferred
Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc
Understanding of timing closure of digital logic/macros in AMS designs/IPs
Experience in critical path planning and crafting
Experience in methodology and/or flow development as well as automation
Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes with strong scripting skills for flow automation; experience with TCL, Python is a plus
Benefits
Equity
Benefits
Company
NVIDIA
NVIDIA is a computing platform company operating at the intersection of graphics, HPC, and AI.
10001+ employees
H1B Sponsorship
NVIDIA has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
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2025 (1877)
2024 (1355)
2023 (976)
2022 (835)
2021 (601)
2020 (529)
Funding
Current Stage
Public CompanyTotal Funding
$4.09BKey Investors
ARPA-EARK Investment ManagementSoftBank Vision Fund
2023-05-09Grant· $5M
2022-08-09Post Ipo Equity· $65M
2021-02-18Post Ipo Equity
Leadership Team
Jensen Huang
Founder and CEO
Michael Kagan
Chief Technology Officer
Recent News
2026-01-16
2026-01-16
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