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Teledyne LeCroy Protocol Solutions Group (PSG) · 2 weeks ago

Staff Logic Design Engineer

Milpitas, CA

Full-time

Onsite

Senior Level, Lead/Staff

7+ years exp

Teledyne LeCroy Protocol Solutions Group is seeking a Staff Logic Design Engineer to join their dynamic team developing leading edge test and measurement products. In this role, you will architect and implement high-performance digital logic for protocol capture, analysis, and emulation, while collaborating with cross-functional teams on FPGA-based systems that decode and analyze high-speed protocols in real-time.

Electrical & Electronic Manufacturing

Hiring Manager

Rebecca Buonadies Stokes

Responsibilities

Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and buffer management

Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource efficiency

Target high-end FPGAs (Xilinx Versal, Intel Agilex); perform synthesis, P&R, timing closure, and resource optimization

Integrate PCIe IP cores, DMA engines, and custom protocol decoders

Build SystemVerilog/UVM testbenches for block and system-level verification

Conduct simulation, waveform analysis, and functional coverage to ensure robust design

Collaborate with hardware, firmware, and software teams to bring up and validate protocol analyzer platforms

Support lab debug using logic analyzers, oscilloscopes, and in-system FPGA tools (ILA/SignalTap)

Create design specifications, interface documents, and verification plans

Participate in design/code reviews and contribute to continuous improvement of design practices

Qualification

Verilog/SystemVerilogFPGA DevelopmentPCIe ProtocolDigital Logic DesignUVMTiming ClosurePythonTclCollaborationDocumentation

Required

BS in EE, CS or Computer Engineering required

MS in EE is a plus

7+ years of experience in digital logic design for FPGA or ASIC

Strong proficiency in Verilog/SystemVerilog RTL design

Experience with one or more of the following protocols: PCIe, CXL, NVMe, USB, SAS, SATA

Experience with Monitoring and/or Test & Measurement tools

Experience with PCIe protocol (Gen4/Gen5/Gen6) and familiarity with TLP/DLLP/PHY layer concepts

Hands-on with FPGA toolchains (Vivado, Quartus, etc.) and timing closure

Knowledge of UVM, assertions, and simulation/debug tools (e.g., ModelSim, Vivado Simulator)

Solid understanding of CDC, clock domain design, and reset strategies

Preferred

Experience with protocol analyzers, packet capture, and timestamping logic

Familiarity with AXI interconnects, memory controllers, and high-speed buffering

Exposure to SERDES, PCIe IP integration, and link training/debug

Scripting experience (Python, Tcl) for automation and test infrastructure

Experience with hardware/software co-design, register maps, and embedded firmware interaction

Prior work in test & measurement or semiconductor validation environments

Company

Teledyne LeCroy Protocol Solutions Group (PSG)

Teledyne LeCroy is a worldwide leader in serial data test solutions, creating advanced instruments that drive product innovation by quickly measuring, analyzing and verifying complex electronic signals.

Founded in 1964

Milpitas, California, US

201-500 employees