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Teledyne Technologies Incorporated · 1 month ago

Staff Logic Design Engineer

Milpitas, CA

Full-time

Onsite

Senior Level, Lead/Staff

$142K/yr - $189K/yr

7+ years exp

Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. They are seeking a Staff Logic Design Engineer to architect and implement high-performance digital logic for protocol capture, analysis, and emulation, working on FPGA-based systems and collaborating with cross-functional teams.

ElectronicsEnergyManufacturingTelecommunications

H1B Sponsor Likely

Responsibilities

RTL Design & Microarchitecture + Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and buffer management. + Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource efficiency

FPGA Development + Target high-end FPGAs (Xilinx Versal, Intel Agilex); perform synthesis, P&R, timing closure, and resource optimization. + Integrate PCIe IP cores, DMA engines, and custom protocol decoders

Verification & Debug + Build SystemVerilog/UVM testbenches for block and system-level verification. + Conduct simulation, waveform analysis, and functional coverage to ensure robust design

System Integration + Collaborate with hardware, firmware, and software teams to bring up and validate protocol analyzer platforms. + Support lab debug using logic analyzers, oscilloscopes, and in-system FPGA tools (ILA/SignalTap)

Documentation & Process + Create design specifications, interface documents, and verification plans. + Participate in design/code reviews and contribute to continuous improvement of design practices

Qualification

Verilog/SystemVerilogFPGA DevelopmentDigital Logic DesignProtocol AnalysisPCIe ProtocolUVMScripting PythonScripting TclContinuous ImprovementTeam CollaborationDocumentation

Required

BS in EE, CS or Computer Engineering required

7+ years of experience in digital logic design for FPGA or ASIC

Strong proficiency in Verilog/SystemVerilog RTL design

Experience with one or more of the following protocols: PCIe, CXL, NVMe, USB, SAS, SATA

Experience with Monitoring and/or Test & Measurement tools

Experience with PCIe protocol (Gen4/Gen5/Gen6) and familiarity with TLP/DLLP/PHY layer concepts

Hands-on with FPGA toolchains (Vivado, Quartus, etc.) and timing closure

Knowledge of UVM, assertions, and simulation/debug tools (e.g., ModelSim, Vivado Simulator)

Solid understanding of CDC, clock domain design, and reset strategies

Preferred

Experience with protocol analyzers, packet capture, and timestamping logic

Familiarity with AXI interconnects, memory controllers, and high-speed buffering

Exposure to SERDES, PCIe IP integration, and link training/debug

Scripting experience (Python, Tcl) for automation and test infrastructure

Experience with hardware/software co-design, register maps, and embedded firmware interaction

Prior work in test & measurement or semiconductor validation environments

Company

Teledyne Technologies Incorporated

Glassdoor3.4

Teledyne Technologies is a leading provider of sophisticated electronic components, instruments & communications products, including defense electronics, data acquisition & communications equipment for airlines and business aircraft, monitoring and control instruments for industrial and environmental applications and components, and subsystems for wireless and satellite communications.

Founded in 1960

Thousand Oaks, California, USA

10001+ employees

http://www.teledyne.com

H1B Sponsorship

Teledyne Technologies Incorporated has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)

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