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Majestic Labs ai · 2 weeks ago

Senior Power Delivery & Integrity Engineer

Los Altos, CA

Full-time

Onsite

Senior Level, Lead/Staff

10+ years exp

Majestic Labs ai is seeking a highly skilled Senior Power Engineer to take a leadership role in defining the power delivery architecture for next-generation AI server platforms. This role involves end-to-end design of power delivery paths, collaborating with various engineering teams to ensure system performance and efficiency.

Artificial Intelligence (AI)Software

Responsibilities

Architect and design board-level, server-level, and rack-level power delivery systems for high-power subsystems

Define PDN topology, including VRMs, POLs, vertical and lateral power routing, and high-current interfaces

Perform component selection (VRMs, FETs, inductors, bulk caps, MLCCs, connectors, busbars) and create derating, margin, and reliability guidelines

Lead decoupling capacitor strategy across package and PCB layers to meet target impedance and transient response goals

Drive power integrity analysis (AC/DC, Z-target, transient, EMI/EMC) and validate designs through modeling, simulation, and lab measurement

Collaborate with mechanical and thermal teams to ensure high-current routing, cooling requirements, and system constraints are aligned

Partner with silicon and package engineering to co-design vertical PDN paths, including socket interfaces, pin/bump maps, and transient load profiles. Review and advise silicon design to improve power integrity

Develop test plans for PDN validation, transient load tests, impedance measurement, and system bring-up

Provide expertise during failure analysis, root-cause investigations, and corrective actions for system power issues

Qualification

Power integrityPDN modelingHigh-current designSPICE proficiencyMeasurement equipmentEMI/EMC mitigationThermal-mechanical co-designRack-level power architecturesCommunication skillsCross-functional collaboration

Required

BS/MS in Electrical Engineering or related field

10+ years of experience in high-power delivery design

Demonstrated experience designing high-current, low-voltage power delivery for SoCs

Deep expertise in power integrity, PDN modeling, VRM design, target impedance definition, and transient response optimization

Proficiency with SPICE, PDN simulation tools (Keysight, Cadence Sigrity/Clarity, Ansys SIwave), and measurement equipment (VNAs, oscilloscopes, electronic loads)

Solid understanding of package-to-PCB PDN interactions

Strong communication and cross-functional collaboration skills