Principal Engineer Microelectronic Semiconductors jobs in United States
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Northrop Grumman Australia · 3 weeks ago

Principal Engineer Microelectronic Semiconductors

Northrop Grumman is a pioneering company in technological advancements, and they are seeking a Principal Microelectronics Semiconductor Metals Process Engineer for their Advanced Packaging Technology facility in Apopka, FL. The role involves providing senior fabrication support and technical direction for semiconductor wafer processes, collaborating with cross-functional teams, and driving process improvements.

Defense & Space
badNo H1BnoteSecurity Clearance RequirednoteU.S. Citizen Onlynote

Responsibilities

Primary metals team leader responsible for all PVD and plasma clean processes, development, and associated metrology. The role will require experience with production deployment across a broad range of tool sets, processes, and wafer sizes
Work closely with cross-functional teams in Process Engineering, Manufacturing, Quality, Integration, and R&D to ensure process stability, improve yield, high-volume ramp, and drive continuous improvement initiatives
Mentor and train junior engineers and technicians on shift to support quality and delivery metrics for operations
Drive process improvements for new technology insertion to improve process robustness and achieve technology milestones for yield, reliability, and cost
Oversee and develop robust, manufacturable process recipes for Foundry customers in PVD, plasma cleaning, and bumping processes, and the associated metrology and analysis using designs of experiments (DOEs) and industry standard methods
Identify, resolve issues, and improve these plating processes to provide maximum quality and process availability
Ensure all metal equipment is properly qualified and calibrated
Define and optimize PVD thin films, plasma cleans, dry etching(metal etch), sphere drop, and redistribution layers for bumping processes in support of new technologies
Develop new technologies across the portfolio of emerging technologies in semiconductor wafer-level interconnect manufacturing on multiple wafer sizes
Execute strategic projects for improvement of sustaining operations through monitoring statistical process control (SPC) charts and disposition of out-of-spec material
Support process control, planning, safety, and quality organizations to ensure the equipment meets cost, quality, safety, and reliability metrics
Use Failure Mode and Effects Analysis (FMEA) to assess and mitigate risk for critical processes, process modules, and tools
Drive process improvements for volume manufacturing using statistical tools, DOE techniques, data-driven decision making, and systematic problem-solving skills
Adhere to all safety regulations and protocols to maintain a safe working environment
Collaborate and drive continuous improvement projects with both equipment vendors and materials suppliers
Support capital equipment projects through procurement, installation, and release for production use
Achieve customer on-time delivery and cycle time commitments through tool qualification and OEE management with manufacturing operations
Coordinates with production on day-to-day activities. Assists in the resolution of production workflow issues
Maintain accurate records of processes/recipes, quality checks, and maintenance activities
Support engineering data analysis, including metrology data, ERP and MES data, and other in-process metrics

Qualification

PVD process controlProcess developmentStatistical Process ControlFailure ModeEffects AnalysisVacuum technologyThin-film stressData analysis techniquesDesign of ExperimentSix Sigma conceptsSafety complianceCommunication skillsTeam leadershipMentoringCollaborationProblem-solvingAttention to detailAdaptability

Required

BS Degree in Materials Science, or a related STEM field with a minimum of (5) years of Semiconductor Metals (PVD) and/or Alloys experience, or (3) years with a master's, or (0) years with a PhD
Proficiency in semiconductor PVD process control and process development
Proficiency in process set-up, optimization, and troubleshooting for PVD, plasma clean, and bumping toolsets
Strong understanding of vacuum technology, thin-film stress, adhesion, uniformity, and contamination control
Experience with under bump metallurgy, and optimizing plasma parameters (RF power, gas chemistry, pressure, bias, time) to achieve residue-free surfaces
Experience fabricating a wide variety of interconnect technologies and metals, including lead and lead-free solders and other metal systems
Experience in a production manufacturing environment
Experience in Design of Experiment (DOE), Statistical Process Control (SPC), and 6 sigma concepts for process development and control
Experience in conducting FMEA analyses of processes and equipment
Experience in technical data collection, organization, and analysis skills
Proficient in data analysis techniques/programs
Familiarity with Enterprise Resource Planning and Manufacturing Execution Systems
US Citizenship is required
The ability to obtain a DOD Secret Clearance is required

Preferred

Experience with JMP, MATLAB, VBA, and/or similar
Expert in 8D Problem Solving
Experience with CAD software (AutoCAD, NX, or similar)
Experience with Minitab software
Experience with SAP MRP software
Strong integration skillset across lithography, plasma descum, wet cleans, electroplating, etch, AOI, and reflow
Characterize surface cleanliness using SEM, FTIR, ellipsometry, contact angle, and XPS
Experience in flip-chip, 2.5D, and 3D packaging
Active Secret Clearance or Higher
Six Sigma Blackbelt Certification

Benefits

Health Plan
Savings Plan
Paid Time Off
Education Assistance
Training and Development
9/80 Work Schedule (where available)

Company

Northrop Grumman Australia

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Northrop Grumman Australia is the Australia-based arm of Northrop Grumman Corporation and committed to generating long-term prosperity, investing in advanced Research & Development, sovereign and exportable Intellectual Property, high-quality jobs and long-term technology leadership across the Commonwealth.

Funding

Current Stage
Late Stage
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