Acceler8 Talent · 4 weeks ago
RTL Design Engineer
Acceler8 Talent is seeking an experienced RTL Design Engineer to join a well-funded startup based out of Mountain View whose hardware promises to drastically change the economics of AI compute for the latest and most demanding models. In this role, you will be responsible for defining microarchitecture and implementing performance-critical RTL that underpins the company’s hardware.
Responsibilities
Design, implement, and debug RTL blocks at the subsystem and full-chip level for custom AI accelerators
Translate architectural specifications into synthesizable, high-performance RTL
Collaborate closely with architecture, verification, physical design, and software teams to ensure correct, performant, and scalable implementations
Optimize RTL for performance, power, and area (PPA) across compute, memory, and interconnect subsystems
Support integration, timing closure, bring-up, and debug through tape-out and silicon validation
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent experience
Strong experience designing RTL in SystemVerilog or Verilog for complex digital systems
Experience implementing performance-critical logic, including pipelines, state machines, memory interfaces, and on-chip interconnects
Solid understanding of computer architecture and micro-architecture, particularly for high-performance compute or accelerator designs
Preferred
Experience working on AI accelerators, GPUs, or high-performance SoCs
Familiarity with hardware–software interfaces, including how RTL design choices impact kernels, compilers, and system software
Experience supporting post-silicon bring-up and debug