Qualcomm · 1 day ago
Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer
San Diego, CA
Full-time
Onsite
Senior Level
$140K/yr - $210K/yr
5+ years expQualcomm Technologies, Inc. is looking for ASIC Design Engineers for their Next Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team. The role involves enabling high speed designs in QCT products through architecture and design responsibilities, including RTL coding and debugging of memory subsystems.
Artificial Intelligence (AI)Generative AISoftwareTelecommunicationsWireless
Responsibilities
Architecture, design (RTL coding), and deployment of the next generation, high-speed memory subsystems into QCT products
Develop or contribute to the development of design specifications
Drive the micro-architecture of portions of the logic design
Implement and deliver RTL
Work with verification engineers to deliver high quality designs
Debugging your designs
Provide debug support when integrated into the rest of the chip
Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis
Make regular contributions to the overall improvement in design methodology to drive productivity and quality of results
Qualification
Required
Bachelor's or Masters degree in Science, Engineering, or related field
5+ years ASIC design, RTL coding, front-end digital design experience
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
Preferred
3-10 years of ASIC design (RTL coding) Preferred
Exposure to RTL Design Verification flows is a plus
Bachelors degree in Electrical or Computer Engineering and at least 5+ years of experience in high speed digital design Master's degree preferred
Experience with LPDDR memory and cache controller, NoC based architectures especially the front end interfacing to the CPU, DSP, and multimedia processors
On-chip tightly coupled SRAM & L3 cache controller architecture/design
Experience with x86 or ARM CPU/bus architectures
Ordering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specification
Benefits
Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
10001+ employees
H1B Sponsorship
Qualcomm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2013)
2024 (1910)
2023 (3216)
2022 (2885)
2021 (2104)
2020 (1181)
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
Leadership Team
Cristiano Amon
President and Chief Executive Officer
I
Isaac Eteminan
CEO
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