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SpaceX · 1 week ago

Sr. Full Chip Physical Design Engineer (Silicon Engineering)

Sunnyvale, CA

Full-time

Onsite

Senior Level

$170K/yr - $230K/yr

5+ years exp

SpaceX is actively developing technologies to enable human life on Mars and is seeking a Sr. Full Chip Physical Design Engineer to join their team. The role involves developing next-generation silicon for deployment in space and ground infrastructures, contributing to the performance and capabilities of the Starlink network.

Advanced MaterialsAerospaceManufacturingNational SecuritySpace Travel

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

Perform SOC top level physical design; floor-planning, I/O, bump & RDL (redistribution layer) planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, partition hardening, chip level clock, feedthrough, special interface, and interconnect planning, bus routing, sequential pipeline planning and top level design for testability (DFT) planning

Collaborate with chip architects, ASIC engineers, package engineers and block level physical design engineers to drive, chip floorplan reviews and identify area, interconnect, IP integration, and floorplan improvement opportunities

Perform chip timing budgeting and constraint pushdown to partition owners

Work with static timing analysis, physical verification, electromigration/voltage drop, noise and other signoff teams to achieve closure and tapeout on time

Run physical verification at chip level and provide feedback and guidance to block level physical design engineers to fix design rule check/layout versus schematic/antenna/electrical rule check/design for manufacturing violations

Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements

Qualification

SOC physical designASIC design experienceEDA tools knowledgeDeep sub-micron designVerilog/System VerilogHigh reliability designScripting skillsCan-do attitudeDynamic group workSelf-driven

Required

Bachelor's degree in electrical engineering, computer engineering or computer science

5+ years of ASIC and/or physical design flow development experience in industry

Preferred

Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)

Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.)

In-depth knowledge of industry standard EDA tools, understand their capabilities and underlying algorithms

Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ

Strong knowledge of deep sub-micron FinFET technology nodes (7nm and below) design problems and solutions (leakage power, signal integrity, etc.) multi-corner and multimode timing closure, process variations, physical verification methodology and tapeout

Familiar with implementation or integration of design blocks using Verilog/System Verilog

Experience with clock domain crossings, DFT/Scan/MBIST/LBIST/JTAG/Boundary-scan testing and understanding impacts on physical design flow

Experience with high reliability design and implementations

Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)

Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment