W2C2C · 18 hours ago
PSV DDR Validation Engineer
Dallas, TX
Full-time
Onsite
Senior Level
5+ years expW2C2C is a company specializing in marketing and submissions for quality profiles, and they are seeking a PSV DDR Validation Engineer for EnCharge AI. The role involves leading the validation of DDR memory subsystems across multiple SoC platforms, developing test plans, and collaborating with design and firmware teams.
Computer Software
Hiring Manager
Naveen Sai Vinjamuri
Responsibilities
Take lead responsibility for validating DDR memory subsystems (LPDDR4x, LPDDR5x) on multiple SoC platforms
Define comprehensive test plans and execute tests covering memory training procedures, performance benchmarks, stress scenarios, timing margin analysis, and overall reliability
Collaborate with design and firmware teams to develop, integrate, and debug firmware essential for memory training
Write necessary firmware components (like bootloaders, memory drivers, test hooks) to enable testing
Integrate and debug firmware for memory initialization and training, specifically on systems using RISC-V or ARM processors
Work closely with software and hardware teams to ensure firmware and hardware components interact correctly
Coordinate with board and Signal/Power Integrity (SI/PI) teams for related evaluations
Utilize standard lab equipment (oscilloscopes, logic analyzers, BERTs, power analyzers) for test execution, data collection, and troubleshooting memory-related issues
Perform root cause analysis for failures
Develop scripts (Python, Perl, C/C++) to automate test procedures and validation workflows
Qualification
Required
Take lead responsibility for validating DDR memory subsystems (LPDDR4x, LPDDR5x) on multiple SoC platforms
Define comprehensive test plans and execute tests covering memory training procedures, performance benchmarks, stress scenarios, timing margin analysis, and overall reliability
Collaborate with design and firmware teams to develop, integrate, and debug firmware essential for memory training
Write necessary firmware components (like bootloaders, memory drivers, test hooks) to enable testing
Integrate and debug firmware for memory initialization and training, specifically on systems using RISC-V or ARM processors
Work closely with software and hardware teams to ensure firmware and hardware components interact correctly
Coordinate with board and Signal/Power Integrity (SI/PI) teams for related evaluations
Utilize standard lab equipment (oscilloscopes, logic analyzers, BERTs, power analyzers) for test execution, data collection, and troubleshooting memory-related issues
Perform root cause analysis for failures
Develop scripts (Python, Perl, C/C++) to automate test procedures and validation workflows
B.E/M. E in Electronics & Communication Engineering
10 to 15 years of experience
10+ years of SOC validation experience
At least 5 years of experience in post-silicon Memory subsystem validation, with a specific focus on LPDDR4x or LPDDR5 memory subsystems
Strong C/C++ programming skills, particularly for low-level code (like hardware abstraction layers) used in system bring-up
Proven experience integrating and debugging firmware in memory validation or general SoC environments
Deep understanding of DRAM operations, memory controller architecture, standard memory training algorithms, and JEDEC LPDDR standards (including timing parameters)
Experience with silicon bring-up processes and associated tools like Lauterbach debuggers, JTAG interfaces, and trace analyzers
Familiarity with embedded operating systems and the typical boot sequences
System-level memory performance tuning and characterization
Lead the development and execution of bring-up and silicon validation test plans for the SoC
Perform validation of SoC peripherals including LPDDRx, PCIe, I2C, and qSPI
Manage and oversee all phases of the validation lifecycle, from initial bring-up to production release
Collaborate closely with cross-functional hardware and software teams to design and implement effective validation and characterization strategies
Develop and integrate software-based test applications for stress testing and SLT screening, working with software teams to assess system performance and hardware/software interactions under diverse conditions
Drive continuous improvement initiatives in validation and productization processes to boost efficiency and ensure high-quality deliverables
10+ years of SOC validation experience
Strong understanding of digital design, circuit design and analysis, computer architecture and SOC architecture
Knowledge of DDR training and memory system operation a plus
Hands-on experience with silicon bring-up, debugging, and characterization of SoC-level IPs (e.g., PCIe Gen 4/5, LPDDR4/5, PLL/DLL, NOR Flash, SPI, I2C, RISC-V processors), with familiarity in memory and I/O interfaces
Proficiency in programming/scripting (C/C++, Perl, Ruby, Python) for automation, test
Experience with Lauterbach Debugger for RISC-V and lab equipment (oscilloscopes, BERT, power supplies, logic analyzers)
Solid foundation in digital design, microarchitecture, timing, power, noise, control systems, and HW/SW interaction, including firmware
Develop end-to-end system validation test plans for the NPU, including characterization
Collaborate with cross-functional teams, including software and hardware engineers, to design optimal test validation and characterization solutions
Create, modify, and refine tests based on a deep understanding of the NPU design, ensuring comprehensive coverage and suggesting improvements where necessary
Lead the development and execution of bring-up, validation, qualification, tuning, and productization plans
Build and integrate necessary tools, scripts, and infrastructure in close collaboration with stakeholders
Spearhead post-silicon bring-up efforts and provide expert support for debugging activities
Drive continuous optimization of validation and productization methodologies to improve overall process efficiency and quality
Minimum 6 years of experience in validating and debugging complex systems
In-depth knowledge of computing architecture, technical debugging, and validation strategies
Strong debugging skills with the ability to analyze complex issues using first principles
Experience with Lauterbach Debugger for RISC-V and lab equipment (oscilloscopes, BERT, power supplies, logic analyzers) is strongly preferred
Solid foundation in digital design, microarchitecture, timing, power, noise, control systems, and HW/SW interaction, including firmware
Proficiency in programming/scripting (C/C++, Perl, Ruby, Python) for automation, test scripting, and GUI development
Preferred
Knowledge of signal and power integrity is a plus
Company
W2C2C
🎯 Online Job Services for Students & Professionals – Join W2C2C Today! At W2C2C, we provide comprehensive online job services to help students, fresh graduates, and experienced professionals connect with top employers and recruiters.
10001+ employees
Funding
Current Stage
Late StageCompany data provided by crunchbase