Castelion · 12 hours ago
PCB Layout Engineer
Castelion is redefining defense development through rapid iteration and modern commercial manufacturing at scale. As a PCB Layout Engineer, you will independently own the layout and release of complex avionics printed circuit boards for hypersonic missile systems, collaborating with various engineering teams to deliver flight-worthy hardware on aggressive schedules.
Responsibilities
Own PCB layout from initial placement through fabrication and assembly release for complex avionics hardware
Translate schematic intent and system requirements into robust, manufacturable PCB layouts
Drive component placement, stack-up definition, routing strategy, and constraint management across analog, digital, RF, and power domains
Lead PCB DFM/DFA reviews with fabrication and assembly vendors; close manufacturing issues through release
Develop and maintain PCB fabrication and assembly packages (Gerber/ODB++, BOMs, drawings)
Interface directly with board houses to select materials, stack-ups, impedance targets, and DFX rules
Ensure designs meet IPC Class 3/3A and Castelion internal design standards
Maintain and expand the PCB component library; contribute to company-wide layout standards and best practices
Support signal integrity, power integrity, and EMI-focused layout trade studies
Collaborate with electrical, mechanical, systems, and software engineers through integration, test, and qualification
Support rapid iteration cycles and hardware re-spins in a fast-paced development environment
Provide technical guidance to junior PCB designers and review peer layouts
Communicate clearly across disciplines and sites to keep hardware on schedule
Qualification
Required
5 – 8+ years of experience in PCB layout and electronics hardware development
Strong proficiency with Altium (preferred) or equivalent professional PCB layout tools
Experience using mechanical CAD tools such as NX or SolidWorks for ECAD–MCAD coordination
Proven experience taking complex PCBs from concept through production release
Experience designing high-density, multi-layer PCBs (typically 10–20+ layers)
Solid understanding of signal integrity, power distribution, grounding, EMI/EMC, and thermal considerations
Experience designing to IPC Class 3 / 3A requirements
Knowledge of PCB fabrication processes, materials, stack-ups, and manufacturing constraints
Experience working directly with PCB fabrication and assembly vendors
Strong problem-solving skills, attention to detail, and ownership mindset
Ability to operate effectively in highly cross-functional engineering teams
Willingness to support extended hours or weekend work during critical integration, test, and flight milestones
To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State
Preferred
Experience in aerospace, missile systems, spaceflight, defense, or other high-reliability hardware environments
Hands-on experience with boards containing: Microcontrollers, DSPs, FPGAs, or ASICs; High-speed digital interfaces (DDR3/4, SerDes, ADC/DACs); Power management and sensor interfaces; RF and mixed-signal circuitry
Familiarity with signal and power integrity tools (e.g., SiWave, HFSS, ADS, CST)
Experience supporting EMI/EMC mitigation through layout techniques
Familiarity with relevant industry standards (e.g., MIL-STD, DO-254)
Experience supporting hardware through environmental testing and qualification
Ability to mentor junior engineers and elevate team layout quality
Benefits
Long-term stock incentives
Comprehensive medical, vision, and dental insurance
Four weeks of paid time off per year
Company
Castelion
Castelion is a defense tech company that applies modern hardware development and manufacturing processes to national security challenges.
Funding
Current Stage
Growth StageTotal Funding
$469.61MKey Investors
Lightspeed Venture PartnersSilicon Valley BankAndreessen Horowitz
2025-12-05Series B· $350M
2025-01-29Series A· $70M
2025-01-29Debt Financing· $30M
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