Apply on Employer Site

Samsung Semiconductor · 1 day ago

Senior Staff Engineer, Layout Design

San Jose, California, United States

Full-time

Onsite

Senior Level, Lead/Staff

$19K/yr - $301K/yr

10+ years exp

Samsung Semiconductor Inc. is a global leader in technology solutions, focusing on advancing the world’s technology. The role involves leading layout engineers and collaborating with design engineers to develop next-generation RF transceivers and mixed-signal circuits for wireless communication systems.

Semiconductor

H1B Sponsor Likely

Responsibilities

Work with design engineers to come up with optimal floorplan in terms of areas and performance

Be able to lead few layout engineers, help them plan, and execute on layout tasks to accomplish complicated layout blocks

Finish layout tasks with good quality

Have good communication skills to collaborate with other design and layout engineers

Track schedule and status regularly to make sure the layout will be finished on time

Working with remote circuit designers to determine the chip floorplan

Come up with strategies to optimize the parasites, reduce area, and improve High Speed SERDES/analog performance

Estimate schedule and come up with plan how to get things done within a dedicated time frame

Read the design document provided by the foundry and figure out how to resolve issues like latch-up and DRC

Perform custom layout using Virtuoso, and be able to get LVS/DRC clean

Be familiar with CAD tools, including Virtuoso, Calibre LVS, DRC, SkillCad and so on

Qualification

RF/Analog circuit layout designAnalog/mixed-signal layout designCADENCE layout toolsCALIBRE DRCERCLVSCustom layout using VirtuosoProgramming in SKILLPerlPythonCuriosityResilienceCommunication skillsLeadership skillsCollaboration skills

Required

Bachelor's Degree with 15+ years, Master's with 13+ years, or PhD's with 10+ years of relevant industry experience in Electrical Engineering, Technical, or related field preferred

Extensive experience in analog/mixed-signal layout design of deep submicron CMOS circuits and recent experience on advance nodes including FinFET technologies

High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, reports

Extensive experience in analog/RF related circuit layout, including LNA/PA/PLLs and etc

High level of proficiency in CADENCE or MENTOR GRAPHICS layout tools

Good communication skills with design leads as well as engineers for schedule planning

Being able to lead a small group of layout engineers to deliver a successful tapeout

Preferred

Programming knowledge in SKILL, Perl, and/or Python is a bonus

Benefits

Medical/Dental/Vision/401k

Charitable giving match

4+ weeks of paid time off a year

Stipend for fertility care or adoption

Medical travel support

Virtual vet care for your fur babies

On-demand apps and free confidential therapy sessions

Onsite Café and gym

Virtual classes

Flexible environment

Company

Samsung Semiconductor

Samsung Semiconductor, Inc. (SSI) is a multi-billion dollar wide range of industry-leading semiconductor solutions.

Founded in 1974

San Jose, California, USA

10001+ employees

https://www.samsung.com/us/samsungsemiconductor

H1B Sponsorship

Samsung Semiconductor has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)

Distribution of Different Job Fields Receiving Sponsorship

Represents job field similar to this job

Trends of Total Sponsorships

2025 (130)

2024 (110)

2023 (153)

2022 (134)

2021 (124)

2020 (134)