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BAE Systems, Inc. · 5 hours ago

Principal FPGA Verification Engineer - $15K Sign On Bonus

Westminster, CO

Full-time

Onsite

Senior Level, Lead/Staff

$116K/yr - $197K/yr

6+ years exp

BAE Systems, Inc. is a leading provider of defense, aerospace, and security solutions. The Principal FPGA Verification Engineer will apply innovative design techniques and verify FPGA designs while collaborating with cross-functional teams to deliver cutting-edge electronic systems for defense applications.

Defense & Space

No H1B

U.S. Citizen Only

Responsibilities

Apply innovative design techniques to create defense-oriented, cutting-edge electronic systems

Work in a fast-paced team environment on a variety of R&D, proof of concept, and production programs

Verify FPGA designs (including SOC architectures utilizing soft-core processors, digital filters, image processing algorithms, and communication interfaces/protocols), design and implement test benches for both unit level and system level environments, and create reusable verification environments that can be used across multiple projects

Work in a System Verilog/UVM environment developing tests, testbenches, UVM components, and regressions/testlists

Be responsible for generating and executing the FPGA Verification Test Plan and FPGA Verification Matrix

Work collaboratively and in tandem with system architects, FPGA design engineers, and embedded software engineers

Maintain a regular and predictable work schedule

Establish and maintain effective working relationships within the department, the Strategic Business Units, Strategic Capabilities Units and the Company. Interact appropriately with others in order to maintain a positive and productive work environment

Perform other duties as necessary

Qualification

FPGA/ASIC VerificationSystem VerilogUVMC++ programmingElectronic circuit designCoverage writingSignal Processing knowledgeCybersecurity knowledgeCommunication skillsPresentation skills

Required

Us Citizenship Required

BS degree or higher in Engineering or a related technical field is required plus 6 or more years related experience

Each higher-level degree, i.e., Master's Degree or Ph.D., may substitute for two years of experience. Related technical experience may be considered in lieu of education. Degree must be from a university, college, or school which is accredited by an agency recognized by the US Secretary of Education, US Department of Education

Solid FPGA/ASIC Verification development methodology

Experience with System Verilog and UVM, and familiarity with electronic circuit design and electronic systems

A solid understanding of object-oriented concepts and experience designing class-based constrained random test benches

Experience with coverage writing (including coverpoints, crosses), coverage collection and improving coverage of the design under test

Good communication skills, as well as excellent presentation skills

A security clearance or access with Polygraph is not required to be eligible for this position. However, the applicant must be willing and eligible for submission, depending on program requirements, after an offer is accepted and must be able to maintain the applicable clearance/access