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Samsung Ads · 4 months ago

Staff Engineer, Coherent Interconnect Design Verification

3900 N Capital of Texas Hwy, Austin, TX, USA

Full-time

Onsite

Senior Level, Lead/Staff

$151K/yr - $227K/yr

6+ years exp

Samsung is a world leader in advanced semiconductor technology, seeking a Staff Design Verification Engineer to lead the functional verification of System IP. The role focuses on design verification, testbench architecture, and collaboration with global teams to enhance Samsung's coherent interconnect IPs for next-generation products.

Marketing & Advertising

Responsibilities

You ensure design excellence and thorough verification by contributing to key features, driving test planning, verifying design feature accuracy, and performing coverage analysis to identify improvement opportunities

You will develop reusable verification environments and testbenches, including stimulus, assertions, checkers, covergroups, and SystemVerilog constraints

You debug and root cause functional fails from regressions, and help with Silicon debug

You perform coverage gap analysis, identifying coverage exclusions and improving stimulus

You will be a key player in test plan and code reviews

You will contribute to power-aware verification with UPF and gate-level simulations

You collaborative with design, SoC, physical design, and performance verification teams to debug failures, resolve spec issues, and enable successful bring-up across IP, SoC, and silicon

You exemplify an ownership culture and inspire an inclusive, high-performing culture by mentoring junior engineers, fostering trust, and data-driven decision-making through open communications

Qualification

Interconnect experienceSystem VerilogUVMARM protocolsGit version controlUnix/Perl scriptingCommunicationCollaboration skills

Required

6+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 4+ years of experience with a Master's degree, or 2+ years of experience with a PhD

Must have experience with Interconnect

Proficiency in ARM protocols – CHI/AXI/ACElite, APB

Expert hands-on coding skills in System Verilog, UVM

Experience with Git version control, Unix/Perl scripting

Excellent communication and collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment