Rambus · 2 months ago
SPE Signal Integrity Engineer
US-San Jose
Full-time
Onsite
Senior Level, Lead/Staff
$152K/yr - $282K/yr
10+ years expRambus is a premier chip and silicon IP provider seeking to hire an exceptional Sr. Principal Engineer with signal integrity and package design experience. The SPE Signal Integrity Engineer will work within the SI/PI team on modeling, analysis, and simulations of signal integrity and power integrity in the DDR field, collaborating with design teams and customers to optimize solutions.
ArchitectureLightingSemiconductor
Responsibilities
Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio
Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis
Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores
Work with our customers to do collaboration to find the optimum SI/PI solution
Help the team during debug and bring up in lab if needed
Solid background in SI/PI and package design to provide technical leadership to the team
Strong interpersonal skill to keep the team motivated and focused
Prior experience in simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces is required
Solid theoretical background and understanding in EM and transmission line theory is a must
Strong background and solid understanding of equalization techniques such as FIR/FFE/DFE/CTLE are required
Must understand package and PCB design, be able to edit APD/Allegro layout files. Know SI/PI driven BGA assignment methodology and be able to simulate for the trade-offs in the context of a system
Extensive experience in correlating simulation results with lab measurements using scopes, TDRs, VNAs etc
Strong understanding of the server system, from CPUs to DRAMs on DIMM modules, is highly desirable
Know the mechanisms of crosstalk and jitter in source-synchronous interfaces and be able to include the effect of such losses into low BER simulations
Proficient with simulations using Spice and ADS
Experience with commercial EDA tools such as ADS, HFSS, Q3D/PowerSI
Familiarity with RedHawk/Totem or XcitePI and Virtuoso is a strong plus
Lab characterization experience of passive components, link margin, or noise using real time/sampling scopes and VNA/TDR is a big plus
Basic knowledge of circuits used in high-speed link design is preferred
Excellent writing and presentation skills are essential as well as good communication skills to work with customers and cross-functional teams
Must be an innovative, self-motivated individual, be able to manage and drive his projects, and must be a team player
Qualification
Required
Solid background in SI/PI and package design to provide technical leadership to the team
Strong interpersonal skill to keep the team motivated and focused
MS or PhD in Electrical Engineering with 10+ years of industry experience in which at least a few years with exposure to DDR4/5
Prior experience in simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces is required
Solid theoretical background and understanding in EM and transmission line theory is a must
Strong background and solid understanding of equalization techniques such as FIR/FFE/DFE/CTLE are required
Must understand package and PCB design, be able to edit APD/Allegro layout files
Know SI/PI driven BGA assignment methodology and be able to simulate for the trade-offs in the context of a system
Extensive experience in correlating simulation results with lab measurements using scopes, TDRs, VNAs etc
Strong understanding of the server system, from CPUs to DRAMs on DIMM modules, is highly desirable
Know the mechanisms of crosstalk and jitter in source-synchronous interfaces and be able to include the effect of such losses into low BER simulations
Proficient with simulations using Spice and ADS
Experience with commercial EDA tools such as ADS, HFSS, Q3D/PowerSI
Familiarity with RedHawk/Totem or XcitePI and Virtuoso is a strong plus
Lab characterization experience of passive components, link margin, or noise using real time/sampling scopes and VNA/TDR is a big plus
Excellent writing and presentation skills are essential as well as good communication skills to work with customers and cross-functional teams
Must be an innovative, self-motivated individual, be able to manage and drive his projects, and must be a team player
Preferred
Basic knowledge of circuits used in high-speed link design is preferred
Benefits
Competitive compensation package
Base salary
Bonus
Equity
Matching 401(k)
Employee stock purchase plan
Comprehensive medical and dental benefits
Time-off program
Gym membership
Company
Rambus
Rambus designs, develops and licenses chip interface technologies and architectures that are used in digital electronics products.
501-1000 employees
H1B Sponsorship
Rambus has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (25)
2024 (16)
2023 (7)
2022 (8)
2021 (3)
2020 (11)
Funding
Current Stage
Public CompanyTotal Funding
$288.57M2023-07-20Acquired
2011-06-07Post Ipo Equity· $88.57M
2010-02-02Post Ipo Equity· $200M
Leadership Team
Luc Seraphin
CEO
Sean Fan
Chief Operating Officer
Recent News
Business Wire
2025-11-05
2025-11-01
Yahoo Finance
2025-10-30
Company data provided by crunchbase