Analog Layout Design Lead jobs in United States
info-icon
This job has closed.
company-logo

Eximietas Design · 3 days ago

Analog Layout Design Lead

positionSan Francisco Bay Area
timeFull-time
remoteOnsite
seniorityLead/Staff
date10+ years exp

Eximietas Design is seeking an Analog Layout Design Lead to drive the physical implementation of high-performance analog and mixed-signal IP. The role involves leading the layout architecture for complex IP and SerDes macros, collaborating with various teams, and mentoring junior engineers.

Artificial Intelligence (AI)Cloud ComputingInformation TechnologyMachine Learning
check
H1B Sponsor Likelynote
Hiring Manager
Mohini Tyagi
linkedin

Responsibilities

Lead and own analog / mixed-signal layout architecture for complex IP and SerDes macros
Execute and review layouts for TX/RX, clock paths, PLL/DLL/CDR, IOs, regulators, bias circuits, and analog datapaths
Define and enforce layout methodology including:
Precision matching, symmetry, shielding, and isolation
Parasitic optimization and noise mitigation
Power grid design, routing guides, density strategies, and metal fill solutions
Drive floorplanning and hierarchical layout strategies to optimize analog performance and scalability
Ensure clean signoff across DRC, LVS, ERC, density, extraction, EM/IR, and reliability flows
Collaborate with PD teams on macro integration and full-chip assembly
Develop or enhance PCell libraries and SKILL-based automation to improve layout productivity and consistency
Mentor and technically guide junior and mid-level layout engineers across global teams
Support silicon debug and correlation, identifying layout-driven performance issues

Qualification

Analog layout designHigh-Speed SerDes layoutAdvanced process nodesCadence VirtuosoSKILL scriptingLayout automationCommunication skillsProblem-solving skillsCross-functional collaboration

Required

10–20 years of hands-on experience in custom analog / mixed-signal IC layout
Proven leadership owning high-impact analog layouts from concept through tape-out
Deep expertise in High-Speed SerDes layout (28G/56G/112G preferred)
Strong experience across advanced process nodes (FinFET 7nm/5nm and below)
Mastery of precision matching and device placement
Mastery of high-current and clock-sensitive structures
Mastery of substrate noise, latch-up, ESD, and reliability considerations
Extensive experience with Cadence Virtuoso, Calibre / Synopsys verification flows, and extraction tools
Proficiency in SKILL scripting, PCell development, and layout automation
Track record of delivering first-pass clean layouts with disciplined scheduling
Strong communication, problem-solving, and cross-functional collaboration skills

Preferred

Experience defining organization-wide layout methodology or training programs
Prior ownership of PLL, clocking IP, or SerDes clock paths
Exposure to post-silicon validation and layout-related debug
Experience working with distributed or offshore layout teams
Familiarity with PCIe, Ethernet, CXL, or similar high-speed protocols

Company

Eximietas Design

twittertwittertwitter
company-logo
Eximietas Design is a technology consulting and solutions development firm.
dateFounded in 2023
location
San Jose, California, USA
people-size501-1000 employees
web-link
https://www.eximietas.design/

H1B Sponsorship

Eximietas Design has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (10)
2024 (3)
2023 (1)

Funding

Current Stage
Late Stage

Leadership Team

leader-logo
Jay Avula
CEO
linkedin
Company data provided by crunchbase