Formal DV Lead Engineer jobs in United States
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Jobs via Dice ยท 2 days ago

Formal DV Lead Engineer

Dice is the leading career destination for tech experts, and they are seeking a Formal DV Lead Engineer for SightSpectrum LLC. The role involves overseeing formal verification processes for various design blocks and IPs, collaborating with design engineers, and developing comprehensive verification plans.

Computer Software

Responsibilities

Working with Silicon's world-class design engineers to develop a formal micro-architecture specification
Developing comprehensive formal verification test plan that includes unique verification requirement
Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture
Crafting novel and creative solutions for modelling and proving robustness of complex design micro-architectures
Developing and implementing re-usable and optimized formal models and verification code base
Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity
Understanding of temporal logic assertions
Experience with at least one formal verification tool (e.g., Cadence Jasper, Synopsys VC-Formal)
Experience with complex verification projects that used formal techniques for closure
Skills in Python, Perl, or Shell scripting (a plus)

Qualification

Formal verificationJasperSV/UVMCode coverageFunctional CoveragesTemporal logic assertionsPythonPerlShell scripting

Required

Design verification
Formal DV
Jasper
Formality
SV/UVM
SoC
IP
Code coverage
Functional Coverages
Working with Silicon's world-class design engineers to develop a formal micro-architecture specification
Developing comprehensive formal verification test plan that includes unique verification requirement
Proving properties of the design
Finding design bugs
Working closely with design teams to help improve the micro-architecture
Crafting novel and creative solutions for modelling and proving robustness of complex design micro-architectures
Developing and implementing re-usable and optimized formal models and verification code base
Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity
Understanding of temporal logic assertions
Experience with at least one formal verification tool (e.g., Cadence Jasper, Synopsys VC-Formal)
Experience with complex verification projects that used formal techniques for closure

Preferred

Skills in Python, Perl, or Shell scripting (a plus)

Company

Jobs via Dice

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Funding

Current Stage
Early Stage
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