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Northrop Grumman · 1 month ago

Principal/ Senior Principal ASIC DFT Engineer - R10215232

Linthicum Heights, MD

Full-time

Onsite

Senior Level, Lead/Staff

$120K/yr - $180K/yr

5+ years exp

Northrop Grumman is a leading provider of mission-enabling solutions for global security, and they are seeking a Principal/Senior Principal ASIC DFT Engineer. This role involves responsibility for DFT aspects of ASIC design, collaborating with various teams, and requires a strong understanding of digital design concepts.

AerospaceData IntegrationManufacturingRemote SensingSecurity

Growth Opportunities

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Responsible for DFT (Design for Testabilty) aspects of ASIC Design thorough understanding of digital design concepts

Responsible with ASIC development process

Knowledgeable in VHDL, Verilog or SystemVerilog RTL coding and be highly proficient in DFT methodologies

Responsible for operating in a team environment and collaborate across the different teams as required to accomplish the goals

Qualification

ASIC DesignDFT methodologiesVHDL/Verilog/SystemVerilogCadence/Mentor toolsMemory BIST/Logic BISTTest pattern generationTechnical problem solvingScripting languagesEffective communicationPresentation skills

Required

Bachelor's degree with 5 years of experience, a Master's degree with 3 years of experience or a Ph.D. with 1 years of experience in Science, Technology, Engineering, Mathematics, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree

U.S. Citizenship is required

Ability to obtain/maintain a clearance once hired

Experience in full product life cycle of ASIC Design

Experience with Cadence and/or Mentor test insertion and ATPG tools

Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTA

Experience with memory BIST and logic BIST

Experience generating test patterns and analyzing and debugging test failures

Experience working with test engineers to implement ATPG vectors on tester hardware

Proficiency in HDL (VHDL/Verilog/SystemVerilog) and scripting languages such as Tcl, Python or Perl

Effective communication and presentation skills and high proficiency in technical problem solving