Meta · 3 days ago
ASIC Engineer, Design Verification
Menlo Park, CA
Full-time
Onsite
Senior Level
$146K/yr - $209K/yr
6+ years expMeta is hiring an ASIC Design Verification Engineer within the Infrastructure organization. The role involves building IP and System On Chip (SoC) for data center applications, focusing on verification closure of design modules and collaboration with cross-functional teams to ensure high design quality.
Computer Software
Responsibilities
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Qualification
Required
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Preferred
Experience with revision control systems like Mercurial(Hg), Git or SVN
Experience with verification of ARM/RISC-V based sub-systems or SoCs
Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation
Experience in development of UVM based verification environments from scratch
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, Ethernet, DDR, HBM
Experience with micro-architectural performance verification
Experience verifying GPU/CPU designs
Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs
Experience working across and building relationships with cross-functional design, model and emulation teams
Track record of 'first-pass success' in ASIC development cycles
Benefits
Bonus
Equity
Benefits
Company
Meta
Meta's mission is to build the future of human connection and the technology that makes it possible.
10001+ employees
Funding
Current Stage
Late StageLeadership Team
Kathryn Glickman
Director, CEO Communications
Christine Lu
CTO Business Engineering NA
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