Creospan Inc. ยท 1 day ago
Silicon Physical Design Engineer
Creospan Inc. is a growing tech collective of makers, shakers, and problem solvers, offering solutions that will propel businesses into a better tomorrow. They are seeking a Silicon Physical Design Engineer to develop and own physical design implementation of multi-hierarchy low-power designs and resolve design and flow issues related to physical design.
Responsibilities
Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes
Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
Power analysis based on netlist
Qualification
Required
Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies
Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge
Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, PTPX, Primepower
5 years of relevant physical design experience
Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions
Experience in chip power analysis
Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques
Experience with Python, TCL, Perl programming
Bachelor degree in Electrical/Computer Engineering or Computer Science
Preferred
MSEE/CS or equivalent experience
Master's Degree preferred but not required