Altera · 1 week ago
Senior Static Timing Analysis (STA) Developer
San Jose, California, United States
Full-time
Onsite
Senior Level, Lead/Staff
$179K/yr - $259K/yr
10+ years expAltera is seeking an experienced Senior Static Timing Analysis (STA) Developer to architect, design, and optimize next-generation timing analysis engines for ASIC and FPGA design flows. This role involves developing high-performance STA engines, enhancing timing analysis algorithms, and optimizing components for accuracy and runtime efficiency.
Enterprise SoftwareManufacturingSemiconductorSoftware
Responsibilities
Architect and develop high‑performance STA engines for ASIC and FPGA design flows
Enhance graph‑based timing analysis algorithms to support complex clock trees, timing exceptions, and multi‑domain clocking
Improve path search algorithms to reduce memory footprint and accelerate timing path generation
Ensure high correlation and competitive performance relative to industry‑leading STA tools
Identify and eliminate runtime bottlenecks across timing and logic optimization flows
Optimize PPA‑critical components to achieve best‑in‑class accuracy and runtime balance
Implement advanced data structures, dynamic memory management, and disk‑caching strategies to support extremely large IC designs (100M+ gates, thousands of clock domains)
Drive multi‑threading enhancements and parallelization strategies for modern compute architectures
Refactor and modernize codebases to improve maintainability, scalability, and multi‑thread performance
Build robust debugging and diagnostic infrastructure to capture detailed customer‑side failure information
Rapidly root‑cause and resolve complex timing and infrastructure issues based on limited customer feedback
Develop and maintain interfaces between STA engines and synthesis, P&R, and other EDA tools
Ensure data integrity and compatibility across internal and external toolchains
Collaborate with synthesis and optimization teams to deliver cohesive end‑to‑end timing closure solutions
Support customer tape‑outs by ensuring STA robustness, accuracy, and runtime efficiency
Work with field teams to diagnose customer issues and deliver timely fixes or enhancements
Contribute to product roadmap discussions based on customer needs and industry trends
Qualification
Required
10+ years of experience in EDA software development, with a strong focus on STA or timing‑related engines
Deep understanding of static timing analysis concepts, algorithms, and data structures
Strong C/C++ development skills and experience with large‑scale, performance‑critical codebases
Experience with multi‑threading, memory optimization, and scalable software architecture
Proven ability to debug complex issues and deliver high‑quality, production‑ready code
Preferred
Experience developing commercial STA tools or timing engines within synthesis/P&R flows
Familiarity with ASIC/FPGA design flows, clocking architectures, and timing exception handling
Background supporting customer tape‑outs or working directly with customer‑reported issues
Knowledge of disk‑caching strategies, distributed computing, or large‑design scalability techniques
Benefits
Incentive opportunities that reward employees based on individual and company performance.
Company
Altera
Altera provides programmable logic devices and design software for various applications. It is a sub-organization of Intel.
1001-5000 employees
H1B Sponsorship
Altera has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (67)
Funding
Current Stage
Public CompanyTotal Funding
unknown2025-04-14Acquired
1988-03-31IPO
Leadership Team
Raghib Hussain
Chief Executive Officer
Recent News
Business Wire
2025-11-25
2025-11-19
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