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Boeing · 1 day ago

Static Timing Analysis (STA) Engineer – (Lead or Senior)

USA - El Segundo, CA

Full-time

Onsite

Senior Level, Lead/Staff

$177K/yr - $239K/yr

5+ years exp

Boeing Space, Intelligence & Weapons Systems is seeking a Static Timing Analysis Engineer to join their Electronic Products team in El Segundo, CA. The role involves handling pre-layout and post-layout timing for digital ICs/SoCs & FPGAs, collaborating with various teams to achieve timing convergence and first pass success.

AerospaceIndustrial

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Responsible for STA analysis and convergence throughout the ASIC cycle

Responsible for finding solution for intricate timing paths (Digital, analog and mixed signal)

Facilitate STA methodology in collaboration with other STA leaders

Generate timing constraints for multiple ASICs and FPGAs

Generate tool independent timing constraints that will work for synthesis, place & route and static timing analysis

Responsible for intricate cross domain timing path closure

Extract timing information from circuit analysis and develop primary input setup/hold timing constraints as well as primary output required arrival time (RAT) and skew timing constraints

Programming skills with Python, TCL, Perl, Unix shell etc

Help train new engineers

Qualification

Static Timing AnalysisASICsFPGAsSynopsys PrimetimeTiming closurePythonTCLPerlUnix shellEDA toolsDesign for testabilityLeadershipCollaborationProblem-solvingSelf-starter

Required

Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement

5 years of experience with timing closure on ASICs and FPGAs

Experience with several ASICs/FPGAs signoff and at least one ASIC tape-out. Good understanding of RTL to GDS flow

Proficiency using Synopsys Primetime (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis

Ability to work with large physical design team to make the timing convergence successful