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Microsoft · 2 days ago

Senior Design Verification Engineer

Austin, TX

Full-time

Onsite

Mid, Senior Level

$120K/yr - $235K/yr

5+ years exp

Microsoft is a leading technology company focused on cloud infrastructure and intelligent solutions. They are seeking a Senior Design Verification Engineer to perform pre-silicon verification for complex IP and collaborate with various teams to enhance the quality and efficiency of their cloud hardware offerings.

Agentic AIApplication Performance ManagementArtificial Intelligence (AI)Business DevelopmentDevOpsInformation ServicesInformation TechnologyManagement Information SystemsNetwork SecuritySoftware

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

Perform pre-silicon verification for complex IP, including creating testplans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage

Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for IP/SS/SOC level verification

Define verification strategy, requirements, test environments for IP/SS/SOC level verification

Create test-plans and write tests to provide complete features coverage

Develop and implement technical solutions to complex quality and design challenges

Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage

Triage and debug testbench, simulation, and emulation fails

Develop Makefiles and scripts for verification infrastructure

Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment

Collaborate with teams across sites and geographies

Qualification

Design VerificationUniversal Verification Methodology (UVM)System VerilogC/C++PythonDebugging RTLAgile DevelopmentCollaborationProblem Solving

Required

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience

Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience

Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience

equivalent experience

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role

This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter

This role will require access to information that is controlled for export under export control regulations

As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status

Preferred

7+ years of technical engineering experience

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field AND 5+ years of technical engineering experience

Master's degree in Electrical Engineering, Computer Engineering, or related field AND 3+ years of technical engineering experience

Doctorate degree in Electrical Engineering, Computer Engineering, or related field

In depth knowledge of verification principles, testbenches, stimulus generation, and UVM based test environments

Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments

Experience with verification for product from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C/C++ and Universal Verification Methodology (UVM)

Scripting language such as Python or Perl or shell scripts

10+ years of design verification experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental

Verification experience for an IP or SS or SOC related to CPUs, VPUs, GPUs, Tensor unit, or similar

Knowledge of System Verilog class, constraints, coverage and assertions

Experience in scripting languages such as Python or Perl

Hands-on experience in Formal property verification, formal verification of computational data path designs