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AMD · 1 day ago

Sr. Silicon Design Engineer

San Jose, CA

Full-time

Onsite

Senior Level

$136K/yr - $204K/yr

5+ years exp

AMD is a company focused on building innovative products that enhance computing experiences across various domains. They are seeking a Senior Silicon Design Verification Engineer to lead verification efforts for high-speed Crypto and Network-on-Chip designs, ensuring quality and performance through comprehensive verification strategies.

Artificial Intelligence (AI)Cloud ComputingComputerEmbedded SystemsGPUHardwareSemiconductor

Growth Opportunities

No H1B

Responsibilities

Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance

Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level

Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs

Develop and execute comprehensive verification plans, including testbenches and test cases

Collaborate with design, architecture, and software teams to define and implement verification strategies

Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification

Mentor and guide junior engineers, fostering a collaborative and innovative team environment

Qualification

Silicon Design VerificationUVMSystem VerilogFormal VerificationSimulation ToolsVerification Management ToolsLeadership SkillsCommunication SkillsTeam Collaboration

Required

Proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs

Strong team players with excellent communication and leadership skills

Capable of positively and strategically influencing design teams to improve overall product quality

Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance

Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level

Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs

Develop and execute comprehensive verification plans, including testbenches and test cases

Collaborate with design, architecture, and software teams to define and implement verification strategies

Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification

Mentor and guide junior engineers, fostering a collaborative and innovative team environment

BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science

Preferred

Proven track record in technical leadership of teams with 5+ engineers

Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analyzed and verified system-level Performance and QoS (Quality of Service) requirements

Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium

Require strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification

Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus

Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management

Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus

Experience with gate-level simulation, power-aware verification is a plus

Experience with silicon debug at the tester and board level, is a plus