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Microsoft · 1 day ago

Principal Silicon DV Engineer

Mountain View, CA

Full-time

Onsite

Senior Level, Lead/Staff

$140K/yr - $275K/yr

8+ years exp

Microsoft is a leading technology company focused on expanding its Cloud Infrastructure and delivering intelligent solutions. The Principal Silicon DV Engineer will lead a pre-silicon verification team, ensuring the development of high-performance custom IP and SoC designs, while collaborating with various teams to optimize Cloud infrastructure.

Application Performance ManagementArtificial Intelligence (AI)Business DevelopmentData ManagementDevOpsInformation ServicesInformation TechnologyManagement Information SystemsNetwork SecuritySoftware

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

Responsible for delivering cutting-edge, custom IP and SoC designs capable of complex, high-performance functions with extreme efficiency

Technically lead a pre-silicon verification team for developing custom IP and Subsystem (SS) components, focusing on architectural and micro-architectural functions and features

Interact with architects and design engineers to create test plans covering verification strategy, test requirements, and test environments for IP- or SS-level verification

Write, execute, enhance, and debug constrained random stimulus, scoreboards, checkers, and assertions to verify design correctness

Develop UVM (Universal Verification Methodology) components to interface between test code and verification simulation environments

Collaborate across verification teams to promote vertical and horizontal reuse of components

Define and implement functional coverage and drive coverage closure

Triage and debug testbench, simulation, and emulation failures

Write makefiles and scripts for verification infrastructure

Apply Agile development methodologies, including code reviews, sprint planning, and feature deployment

Provide technical leadership through mentorship and teamwork

Qualification

Design VerificationUniversal Verification Methodology (UVM)C++Artificial Intelligence (AI)Machine Learning (ML)Scripting PythonScripting PerlFormal Property VerificationAgile MethodologiesTechnical LeadershipCross-functional Collaboration

Required

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter

This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable

Preferred

9+ years of experience in design verification with a proven track record of delivering high performance IP, SS or SOC testbenches

Experience with verification for multiple product cycles from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C++ and Universal Verification Methodology (UVM)

Experience debugging Register Transfer Level (RTL) designs as well as simulation and/or emulation environments

12+ years of experience in design verification

5+ years experience with lead roles across cross-functional / cross-time-zone engineering teams

Verification lead experience for an IP or SS related to CPUs, VPUs, GPUs, Direct Memory Access (DMA) engine, Tensor unit, or similar

Experience of working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs

Experience in Scripting language such as Python or Perl

Hands on experience in Formal property verification