Stathera, Inc. · 1 day ago
Analog/Mixed-Signal IC Design Engineer
Stathera, Inc. is a fabless semiconductor company specializing in MEMS-based timing solutions. They are seeking a Senior Analog/Mixed-Signal IC Design Engineer to design ASICs and contribute to the full cycle of circuit design and development, including testing and debugging.
Semiconductor
Responsibilities
Work in a newly formed team, designing a full ASIC from scratch
Contribute to all aspects and the complete cycle of circuit design & development
Define the required tests and the verification methodology
Debug the circuits (pre- and post-layout), to achieve the required performance
Help with the post-silicon debug, and ASIC/MEMS integration
Qualification
Required
MS with 5+ years of relevant experience, OR Ph.D. with 2+ years of industry experience designing analog and mixed-signal circuits
Analog-oriented circuit designer, excited about working on a full-chip design
Knowledge and design experience with analog circuits such as bandgap, regulator, data converters, clock generators, and switched-capacitor circuits
Good understanding of signal processing concepts, both continuous and discrete time
Proficient with schematic capture tools such as Cadence Virtuoso or Synopsys Custom Compiler and Spice-based circuit simulators such as Spectre and HSpice or AFS
Decent knowledge of design flow, testing methodology, block-level specifications, calibration & compensation, etc
Familiar with the layout design concepts (parasitic effects, symmetry, regularity and matching, gradient and proximity effects, reliability, etc.)
Preferred
Experience using scripting languages (Shell, PERL, Python, TCL, etc.)
Experience with analog circuit modeling in Verilog or VerilogA
Experience with Matlab and Simulink
Benefits
Group Benefits Plan
ICHRA Allowance
Employee Stock Ownership Plan
Annual personal days
Accrued vacation days
Company
Stathera, Inc.
Stathera is transforming the legacy quartz timing market with MEMS technology designed for the precision, scalability, and integration needs of AI, data centers, and connected devices.
Funding
Current Stage
Early StageTotal Funding
$14.82M2023-05-18Series A· $14.82M
Recent News
2025-04-02
2025-02-11
2025-02-11
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