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Samsung Ads · 1 day ago

Senior Staff Physical Design Feasibility Engineer

3900 N Capital of Texas Hwy, Austin, TX, USA

Full-time

Onsite

Senior Level, Lead/Staff

$180K/yr - $270K/yr

8+ years exp

Samsung is a world leader in advanced semiconductor technology, and they are seeking a Senior Staff Physical Design Feasibility Engineer to drive the performance, power, and area of complex ASIC and interposer designs. This role involves providing technical leadership and optimizing GPU design modifications to meet critical targets.

Marketing & Advertising

Responsibilities

Play a crucial role in driving the overall performance, power, and area (PPA) of complex ASIC and interposer designs, focusing on ensuring their feasibility and success from initial floor planning through to tape-out and sign-off

Providing technical leadership, collaborating across teams, and optimizing and validating GPU design modifications to meet critical timing, power, area, and reliability targets, all of which present exciting technical challenges

You are highly skilled at testing various features and design modifications

You enjoy ensuring frequency, power, and area requirements meet or exceed expectations

You are a self-motivated problem solver who excels at conducting physical design builds to validate design changes

You are a lifelong learner driven by the boundless opportunities, with a keen understanding of the SoC/ASIC design flow using the latest industry-standard placement and routing tools

You are an expert in block-level floor planning and PPA (power, performance, area) optimization

Qualification

Physical design methodologiesPPA optimizationDigital design experiencePhysical design toolsScripting skillsStatic timing analysisSignal integrityPower integrityCommunication skills

Required

10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master's degree, or 6+ years of experience with a PhD

Excellent scripting/programming skills in TCL, Perl, Shell, and/or Python

Skilled knowledge of logical equivalence checking, timing constraints, and Verilog

10+ years of experience in digital or physical design, with a strong background in advanced node physical design methodologies

Proficiency with industry-standard physical design tools, including Cadence Innovus, Synopsys IC Compiler, Mentor Graphics Calibre, Ansys PowerArtist, Siemens EDA Xpedition for synthesis, P&R, STA, and physical verification

Strong understanding of static timing analysis (STA), signal integrity (SI), and power integrity (PI)

Outstanding communication skills and the ability to think and communicate effectively at different levels of abstraction