Testbench Verification Engineer (100% Remote) jobs in United States
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VIVA USA Inc. ยท 5 days ago

Testbench Verification Engineer (100% Remote)

positionUnited States
timeContract
remoteRemote
seniorityMid, Senior Level

VIVA USA Inc. is seeking an experienced Testbench Verification Engineer to join their team. The role involves developing and enhancing UVM-based testbenches, collaborating with various teams, and ensuring optimal behavior of testbenches within complex designs.

ConsultingInformation TechnologyIT InfrastructureSoftware
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H1B Sponsor Likelynote

Responsibilities

Develop, refactor and enhance UVM-based testbenches to verify or accelerate the simulation of complex designs at component or subsystem level
Work closely with other verification engineers, designers, architects, and performance engineers to understand and enhance the behavior of the testbench or related models
Perform tasks related to regression testing, debug and integration of any changes into the main codebase
Ensure optimal behavior of the testbench within the context of the block, chip and overall system
Execute test plans for constrained-random and directed tests, new checks and functional coverage
Provide technical guidance and innovative ideas to improve quality, processes and productivity

Qualification

System VerilogUVMVerification flowsPerformance analysisDebugging testbenchScripting languagesAnalytical problem-solvingAttention to detailCommunication

Required

Exceptional programming skills
System Verilog and UVM experience
Proven experience with working in complex testbench environments
Knowledge of the design verification cycles
Attention to detail
Staying organized
Tracking work to completion
Excellent communication skills
Analytical problem-solving skills
Connecting the dots in new initiatives
Experience in performance verification
Performance debug
Any kind of modeling
Comfortable working across geographies and timezones
Collaborating with multiple teams as needed
Proficient in verification and testbench flows
Deep understanding and hands-on experience in System Verilog and UVM frameworks and testbenches
Proficient in debugging testbench and RTL code using simulation tools
Proficient in the use of Linux-based tools and scripting in Perl, Python and Ruby
Automating workflows in a distributed compute environment
Experience in approaches to simulation profile, efficiency improvement, acceleration
Development of reusable and maintainable code using software engineering best practices
Performance analysis
Performance debug and modeling exposure
Good working knowledge of SystemC and TLM with some related experience
Scripting language experience; Perl, Python, Ruby, Makefile
Verification, testbench flows, System Verilog, UVM
Experience with performance analysis, performance optimization, performance debug
Proven experience in debugging the test-bench, VIP, RTL code

Preferred

Familiarity with the Fabric, NOC solutions is a bonus

Company

VIVA USA Inc.

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VIVA USA Inc. (VIVA), certified Woman and Minority Owned, is a Technology and IT consulting company based in the greater Chicago area.
dateFounded in 1996
location
Rolling Meadows, Illinois, USA
people-size501-1000 employees
web-link
https://www.viva-it.com

H1B Sponsorship

VIVA USA Inc. has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (4)
2024 (9)
2023 (9)
2022 (3)
2021 (14)
2020 (13)

Funding

Current Stage
Late Stage

Leadership Team

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Vinu Ilangovan
Chief Technology Officer
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Company data provided by crunchbase