Scalence L.L.C. · 1 day ago
Hardware Design Engineer 5
Scalence L.L.C. is a dynamic company working on cutting-edge projects that accelerate the storage and networking flow in the cloud. As a key contributor to the Azure Core team, you will analyze information for project planning and execution, and create and modify environments to verify features in a UVM simulation environment.
Information Technology & Services
Responsibilities
Analyze information for project planning and execution
Create and modify environments and components to verify features in a UVM simulation environment
Build, test, and modify product prototypes using working models or theoretical models constructed with computer simulation
Monitor functioning of equipment and make necessary modifications to ensure system operates in conformance with specifications
Qualification
Required
10 years of experience in the hardware engineering field
10 years of experience in UVM and System Verilog programming languages
Experience in IP level verification using UVM and System Verilog within the last 3 years
Experience in AMBA AXI protocol
Basic knowledge of Verilog RTL programming language
Experience with ASIC or FPGA based verification
Preferred
Knowledge of AMBA AXI protocol
Basic knowledge of Verilog RTL programming language
Experience with ASIC or FPGA based verification
Benefits
Inclusive and diverse workplace.
Opportunities for professional growth and development.
Supportive and collaborative team environment.
Company
Scalence L.L.C.
In today’s dynamic and competitive market, success hinges on mastering three key areas: Data Intelligence, Business Resilience, and Digital Experience.
Funding
Current Stage
Late StageCompany data provided by crunchbase