Samsung Ads · 3 weeks ago
Staff Engineer, Static Timing Analysis
3900 N Capital of Texas Hwy, Austin, TX, USA
Full-time
Onsite
Senior Level, Lead/Staff
$151K/yr - $227K/yr
6+ years expSamsung, a world leader in advanced semiconductor technology, is seeking a Staff Static Timing Analysis Engineer to ensure timing integrity and signoff readiness for next-generation GPU IPs. The role involves collaborating with various teams to develop and implement timing analysis strategies for complex GPU designs, while also contributing to technical excellence and maintaining high-quality timing closure.
Marketing & Advertising
Responsibilities
You execute hands-on static timing analysis at top level, developing, debugging, and maintaining timing constraints, clock definitions, and timing environments for complex, multi-clock GPU IPs across functional and test scenarios
You support timing closure and signoff readiness by analyzing timing paths, understanding different clocking and implementation styles, managing latency and skew tradeoffs, and applying timing budgeting, derating, and multi-voltage methodologies across advanced process nodes
You help advancing cross-functional collaboration with RTL, physical design, and SoC teams to identify, debug, and resolve timing issues impacting block-level and full-chip closure, ensuring alignment between logical intent and physical implementation
You contribute to technical excellence by applying and help influencing STA methodologies and sign-off flows, leveraging industry-standard tools and exploring best practices—including POCV, multi-corner analysis, and low-power constraints—to improve timing quality, convergence, and predictability
You take initiatives on moderate-to-complex projects, communicating openly, documenting analysis and results, demonstrating strong ownership and continuous learning mindset by staying ahead of emerging GPU technologies
Qualification
Required
6+ years of experience with a Bachelor's Degree in Computer Science/Engineering, or 4+ years of experience with a Master's Degree, or 2+ years of experience with a Ph.D
Solid understanding and hands-on experience with ASIC design flows and electrical engineering fundamentals
Working knowledge and experience with POCV, derating methodologies, and timing analysis
Strong hands-on experience with industry-standard STA tools (e.g. PrimeTime, Tempus)
Solid hands-on experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs
Working knowledge of formal equivalency checks, low-power checks, timing constraints, UPF
Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python
Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach
Excellent written and verbal communication skills for documenting designs, methodologies, and best practices
Excellent collaboration skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global team environment
Preferred
Familiarity with advanced FinFET process nodes (5nm or smaller)
Hands-on experience with synthesis, block and/or full chip implementation with the latest industry P&R/STA flows and tools
Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure
Benefits
Medical
Dental
Vision
Life insurance
401(k)
Onsite lunch
Employee purchase program
Tuition assistance (after 6 months)
Paid time off
Student loan program
Wellness incentives
MBO bonus compensation
Long term incentive plan
Relocation
Company
Samsung Ads
Samsung Ads helps consumers discover relevant content and brands across Smart TVs, mobile, and desktop.
501-1000 employees
Funding
Current Stage
Late StageLeadership Team
Kimberly Lauterbach
Head Of Business Operations
Recent News
2025-12-16
2025-12-15
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