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Partcl · 19 hours ago

Backend EDA Compiler Engineer

San Francisco, CA

Full-time

Onsite

Mid, Senior Level

$130K/yr - $300K/yr

Partcl is developing the next generation of chip design automation tools with a focus on performance, scalability, and productivity. They are seeking an engineer to design core intermediate representations and build compiler-like pipelines for physical-design tools, ensuring high performance and correctness in chip design processes.

AI InfrastructureArtificial Intelligence (AI)Generative AISemiconductor

Responsibilities

Design the core intermediate representations that physical-design tools use to reason about chips

Build compiler-like pipelines that lower, normalize, and transform design data across stages (netlist → floorplan → PnR → sign-off)

Architect the physical-design data model as a first-class IR, not just a storage format

Create high-performance loaders, serializers, and transformation passes for LEF/DEF, Liberty, SPEF, GDS

Develop APIs that make analysis and optimization passes fast to write and reason about

Own correctness invariants: name resolution, scoping, units, coordinate systems, legalizations, constraints

Optimize for query latency, cache locality, memory layout, and parallel traversal

Build validation and rewriting passes that catch inconsistencies and automatically repair design data

Work directly with PnR, STA, and optimization engineers to co-design new IR features and passes

Treat the database as a compiler backend, not a dumping ground

Qualification

CompilersIR designChip backend conceptsPhysical-design file formatsRust programmingPython programmingData structures designIncremental computationCorrectness reasoningFixing corner cases

Required

Strong background in compilers or IR design (LLVM, MLIR, TVM, CIRCT, or equivalent experience)

Deep familiarity with chip backend concepts: floorplanning, placement, routing, CTS, extraction

Fluency with physical-design file formats: LEF/DEF, Liberty, SDC, SPEF, GDS

Proficiency in Rust for low-level systems work; Python for tooling and pipelines

Experience designing data structures for large graphs / sparse relations / geometric data

Understanding of incremental computation, dependency tracking, and versioning of IR states

Ability to reason about correctness, determinism, and reproducibility in complex toolchains

Comfortable digging into massive designs and fixing pathological corner cases

Preferred

Experience with CIRCT/MLIR or custom EDA IRs

Prior work on static analysis, transformation passes, or compiler runtimes

Knowledge of timing models (CCS/LVF) and constraint propagation

Experience with columnar or in-memory formats (Apache Arrow, Parquet, custom SOA layouts)

Parallel compiler / GPU acceleration experience

Prior ownership of a large-scale EDA database (OpenDB, OA, Innovus/Milkyway internals, etc.)

Company

Partcl

Partcl uses AI and GPUs to optimize chip design and speed up timing analysis workflows.

Founded in 2024

San Francisco, California, USA

2-10 employees

https://partcl.com/

Funding

Current Stage

Early Stage

Total Funding

unknown

Key Investors

Y Combinator

2025-04-01Pre Seed

Leadership Team

William Salcedo

CEO

Vamshi Balanaga

Co-Founder and CTO

Company data provided by crunchbase