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Teradyne · 2 days ago

Package Design Engineer (Semi Test Engineering; North Reading, MA)

North Reading, MA

Full-time

Onsite

Senior Level

$111K/yr - $178K/yr

7+ years exp

Teradyne is the global test and automation specialists, powering next-generation technologies through sophisticated solutions. They are seeking a Package Design Engineer with specialty in Signal and Power Integrity to develop measurement ASIC products and participate in the hardware design workflow.

Consumer ElectronicsIndustrialIndustrial Automation

No H1B

Responsibilities

Develop measurement ASIC products

Participates as a key person in the hardware design workflow necessary to physically realize complex rf, analog, digital and mixed-signal circuits at both chip, package and board assembly level

Serves as a primary interface function between the ASIC Design Team and system hardware engineering and manufacturing teams

Play an important role in all phases of hardware development from providing assessments on architectural feasibility

Planning for signal and power integrity package signoff validation

Performing detailed package and system interconnect optimization and constraint development

Working with the PCB design team to insure that performance and manufacturability targets are met

Collaborating with hardware engineering to insure that our simulation models and methodologies can be validated against functional prototypes

Assist with the capture, tracking, and closure of action items resulting from design review meetings

Qualification

Signal IntegrityPower IntegrityPCB DesignAnalog Circuit DesignRF Circuit DesignCadence SigrityAnsysHigh-Speed Digital SignalingIBIS ModelsTest EquipmentAnalytical SkillsAttention to DetailCommunication SkillsProblem-Solving SkillsTeam Collaboration

Required

A minimum of a MSEE is required, and 7 years of related industry experience

Understanding in the areas of electromagnetic field and transmission line theory, reflection and static timing characterization, PCB and IC Package design for power integrity, high speed digital signaling, analog and RF circuit design

Experience with the modeling of integrated circuits for signal integrity and timing characterization

Familiarity with IBIS models and the application of the IBIS version 7.0 Standard

Simulation and modelling with Cadence Sigrity, Ansys, Hyperlynx, or ADS

5 years of experience working on ATE and test strategies for accurate measurement of high-speed signals and power distribution networks

Understanding of how to go about analyzing passive channels in both time and frequency domain

Experience with concepts of PCB/Package design, design processes, PCB/Package fabrication and materials technology

Familiarity with schematics and constraint driven HW design and development to ensure performance and quality

Experience with the use of test equipment including Vector Network Analyzer, TDR and high-speed oscilloscopes to validate simulation results and models developed from simulation

Familiar with S/ABCD/Z/Y- parameter network characterization and ability to apply it to design for highspeed signal and power integrity

Simulation and characterization of Power Distribution Networks, Target Impedance, and DC IRDrop, Joule Heating

Acute attention to detail with excellent organization skills

Ability to assist with the capture, tracking, and closure of action items resulting from design review meetings

A solid understanding of the fundamentals of EM and transmission line theory and its application to PCB design, particularly for signal integrity concerns, impedance control / matching, and EMI/EMC mitigation

A high degree of efficiency using PCB CAD tools with Cadence experience preferred

Strong analytical, diagnostic and problem-solving skills

Proficient in the use of MS Word, Excel, and web-based applications

Good written communication skills

Experience delivering presentations in support of design reviews

Possess the ability to interface with various stakeholders including Package Aggregators, Package Substrate and PCB assembly and fabrication, manufacturing engineers, design engineers, and supply line personnel

Preferred

Knowledge of Cadence Spectre, and SPICE variants (Pspice, Hspice, etc) is a plus

Knowledge of cutting-edge EDA tools. (Cadence Allegro board design and Concept schematic entry preferred. Allegro Aurora Board Level Signal and Power Integrity Simulation and physical design environment. Virtuoso, Spectre, Hspice, Pspice are a plus)

Experience with the use of time and frequency domain simulation tools and models for full Board level Signal and Power Integrity characterization. Use of 2D and 3D quasi-static, electro-static and full-wave electromagnetic field solvers such as Cadence/Sigrity or Clarity, and board level simulation with Allegro Sigrity SI and PI or Aurora are a plus

A solid understanding of High Voltage engineering and layout expertise of 1kV or higher a plus

Programming skills (Tcl, Python, Perl, MATLAB, C/C++, C#, Visual Basic, etc) for data analysis and test/simulation automation a plus