Altera · 22 hours ago
Design Verification Engineer
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
$200K/yr - $270K/yr
12+ years expAltera is a global leader in programmable logic solutions, delivering cutting-edge FPGA, SoC FPGA, and adaptive compute technologies. The Design Verification Engineer will provide technical leadership in the verification of complex designs, ensuring functional correctness and quality of next-generation products.
Enterprise SoftwareManufacturingSemiconductorSoftware
Responsibilities
Serve as a technical leader for design verification efforts across complex FPGA, SoC FPGA, and IP-level designs
Define, architect, and drive end-to-end verification strategies, plans, and methodologies for large-scale designs
Develop and maintain advanced SystemVerilog/UVM-based verification environments, testbenches, checkers, and coverage models
Collaborate closely with architecture, RTL design, firmware, and software teams from pre-architecture through post-silicon validation
Lead debug and root-cause analysis of complex functional issues at block, subsystem, and full-chip levels
Drive verification signoff using functional coverage, code coverage, assertions, and formal verification where applicable
Mentor and technically guide senior and junior verification engineers, influencing best practices across teams
Evaluate and introduce new verification technologies, tools, and methodologies to improve quality and productivity
Partner with cross-functional stakeholders to ensure alignment on requirements, schedules, and quality metrics
Qualification
Required
12+ years of hands-on Design Verification experience in FPGA, ASIC, or SoC development environments
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (Master's or PhD preferred)
Expert-level proficiency in SystemVerilog and industry-standard verification methodologies (UVM)
Strong experience developing constrained-random, coverage-driven verification environments
Deep understanding of digital design fundamentals, RTL design concepts, and verification signoff criteria
Experience with industry-standard EDA simulation, debug, and coverage tools
Proven ability to lead technically complex verification efforts and influence design and verification strategy
Preferred
Experience verifying FPGA architectures, programmable logic fabrics, or high-speed IP (e.g., PCIe, Ethernet, DDR, SerDes)
Hands-on experience with assertion-based verification and/or formal verification techniques
Familiarity with hardware/software co-verification and embedded firmware interactions
Experience supporting post-silicon validation and debug
Prior experience in a technical lead or principal-level role within a semiconductor organization
Benefits
Incentive opportunities that reward employees based on individual and company performance
Company
Altera
Altera provides programmable logic devices and design software for various applications. It is a sub-organization of Intel.
1001-5000 employees
H1B Sponsorship
Altera has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (67)
Funding
Current Stage
Public CompanyTotal Funding
unknown2025-04-14Acquired
1988-03-31IPO
Leadership Team
Raghib Hussain
Chief Executive Officer
Recent News
Business Wire
2025-11-25
2025-11-19
Company data provided by crunchbase