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Ambiq · 3 days ago

Staff Engineer - Timing Methodology

Austin, Texas, United States

Full-time

Onsite

Senior Level, Lead/Staff

5+ years exp

Ambiq is a leading provider of ultra-low-power semiconductor solutions, focused on enabling intelligence everywhere. The Staff Engineer - Timing Methodology will be responsible for timing closure, defining methodology, and driving constraints in collaboration with RTL and IP vendors, ensuring pre-si timing correlates well to post-si.

Consumer ElectronicsInternet of ThingsManufacturingSemiconductor

Growth Opportunities

No H1B

Responsibilities

In-depth expertise on Timing Methodology and Timing closure both at block level and SOC level in modern Finfet and multi-patterning based process technologies using Cadence Tempus or Synopsys Primetime

Own all aspects of timing convergence, including Signoff to build timing correlation, PVTRc corner definition, timing margining, extraction, signoff timing analysis, glitch noise analysis, timing ECOs and interplay and tradeoff with power

Own, define and drive constraints in collaboration with RTL and IP Vendors.Have in-depth understanding of all timing collaterals for different type of Ips, namely, hard IP, Stdcell and Memory etc

Partner with post-si bringup and testing to ensure pre-si timing correlates well to post-si

Collaborate closely with RTL designers, DFT and other stakeholders to achieve best in class PPA

Continuously improve timing analysis methodologies and scripts to enhance efficiency and flow consistency. Stay at the forefront of advancements in STA and new process nodes

Qualification

Timing AnalysisStatic Timing AnalysisCadence TempusSynopsys PrimetimeDigital Circuit DesignEDA ToolsScripting LanguagesProblem-SolvingTeam CollaborationCommunication SkillsContinuous Learning

Required

Master's degree in Electrical Engineering or Computer Engineering (or a related field)

Minimum of 5 years of experience in Timing Analysis and convergence

Proven expertise in static timing analysis using industry standard timing tools like primetime (Synopsys) or tempus (Cadence)

In-depth understanding of digital circuit design principles and concepts

Strong proficiency with industry-standard EDA tools (e.g., Synopsys, Cadence)

Excellent analytical and problem-solving skills

Ability to work effectively in a team environment and communicate complex technical concepts clearly

Experience with scripting languages (e.g., TCL, Python)

Must be currently authorized to work in the United States for any employer. We do not sponsor or take over sponsorship of employment visas (now or in the future) for this role