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Intel Corporation · 1 day ago

DFT Application Engineer

US, California, Santa Clara

Full-time

Hybrid

Mid Level

$122K/yr - $232K/yr

3+ years exp

Intel Corporation is a leader in semiconductor technology, dedicated to transforming the industry through advanced solutions. The DFT Application Engineer will provide technical support to customers, ensuring successful tape-outs and high-quality standards in DFT methodologies.

Semiconductors

Growth Opportunities

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Provide comprehensive DFT tool/flow/methodology support to address customer issues and challenges, ensuring successful tape-outs and maximum customer satisfaction

Work closely with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors to resolve complex technical issues

Deliver customer-facing technical support and guidance on DFT implementation strategies

Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations

Collaborate with RTL and Hard IP designers on DFT/DFM implementation methodology and work with physical designers on DFT/DFM physical implementation, validation, and timing signoff

Develop and optimize DFT insertion flows for advanced CMOS processes and multi-die designs

Develop application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams

Create best practice guidelines and methodology documentation for DFT implementation across various design complexities

Support knowledge transfer and capability building for both internal teams and customer organizations

Qualification

ASIC DFT/DFM insertionATPG validationAdvanced CMOS processesScripting languagesEDA tools proficiencyAnalyticalCustomer-focusedSelf-motivatedCollaborativeCommunication

Required

US Citizenship required

Ability to obtain US Government Security Clearance

Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field

3+ years of experience with advanced CMOS processes (22nm and below)

3+ years of combined experience in the following: implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at both ASIC design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC level

2+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting)

Preferred

Active US Government Security Clearance with a minimum of Secret Level

Post-graduate degree in Electrical/Computer Engineering or STEM-related field

Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability

Proficiency with major EDA tools for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single die and multi-die designs

Experience building/developing quality DFT/DFX insertion flow and ATPG validation flow

Experience providing technical direction to engineering teams and customer support

Customer-facing experience in technical roles

Experience with state-of-the-art process technology (7nm and below) and PDK-based technology evaluation