Intel Corporation · 19 hours ago
Senior Silicon Application Engineer (Packaging Design)
US, California, Santa Clara
Full-time
Hybrid
Senior Level
$164K/yr - $312K/yr
7+ years expIntel Corporation is dedicated to transforming the global semiconductor industry through its Foundry Services. The Senior Silicon Applications Engineer (Packaging Design) will focus on advanced packaging technologies, working closely with customers to develop and implement design tools and methodologies.
Semiconductors
No H1B
Security Clearance RequiredU.S. Citizen Only
Responsibilities
Establish technical credibility, building trust and strong relationships with Intel Foundry ADG customers
Ensure customers successfully evaluate, adopt, and design products using Intel process technology
Serve as primary technical expert on packaging design tools and implementation methodologies
Provide clear communications and technical guidance to customers and stakeholders
Analyze customer design issues and environments to define functional specifications for EDA vendors
Drive adoption of advanced packaging verification methodologies including signal integrity and power integrity
Work closely with customers on advanced packaging technologies including multi-die/3DIC platforms
Support design implementation and verification across complex packaging architectures
Consult on packaging design challenges and provide innovative technical solutions
Synthesize complex technical information and lead in-depth tactical discussions with customers
Collaborate with Intel engineering teams to address customer requirements and technical challenges
Support customer evaluations and design reviews for advanced packaging implementations
Drive results through highly organized, analytical approach and strong teamwork
Qualification
Required
US Citizenship required
Ability to obtain US Government Security Clearance
Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field
7+ years of experience in Package Design and relevant EDA tools
Experience interfacing with customers and/or stakeholders
Experience analyzing customer design issues, environments, and defining functional specifications for EDA vendors
Preferred
Active US Government Security Clearance with a minimum of Secret Level
Post-graduate degree in Electrical/Computer Engineering or STEM-related field
Experience with Advanced EDA Tool
Experience with Multi-die/3DIC Platform Tools: Cadence Integrity, Synopsys 3DIC Compiler, Siemens Xpedition Substrate Integrator/Innovator 3D
Experience with Implementation Tools: Cadence Virtuoso/Innovus, Allegro (APD/SiP), Siemens Mentor Xpedition, Synopsys Fusion Compiler
Experience with Verification Tools: Siemens Calibre, Synopsys ICV, Cadence Pegasus
Experience with design for verification and performance including Package Signal Integrity, Power Integrity, manufacturing, and yield optimization
Proficiency in scripting languages (Tcl, Python, SKILL, VBScript) for design flow automation and efficiency improvements
Deep understanding of advanced packaging architectures and system-level design challenges
Benefits
Competitive pay
Stock bonuses
Benefit programs which include health, retirement, and vacation
Company
Intel Corporation
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside.
10001+ employees
Funding
Current Stage
Late StageLeadership Team
Brea Watts, MFA
Communications Manager, CEO
Carol Bartz
CEO
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