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Intel Corporation · 22 hours ago

Senior Physical Verification Application Engineer

US, Arizona, Phoenix

Full-time

Hybrid

Senior Level

$150K/yr - $285K/yr

5+ years exp

Intel Corporation is a leader in semiconductor technology, dedicated to transforming the global semiconductor industry. The Senior Physical Verification Application Engineer provides specialized technical support to customers on layout verification and parasitic extraction, ensuring successful customer tape-outs and driving quality improvements in design kits.

Semiconductors

Growth Opportunities

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges

Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolution

Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations

Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams

Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outs

Develop best practice guidelines for physical verification flows and methodologies across advanced process technologies

Lead optimization of physical verification flows for advanced CMOS processes (22nm and below)

Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations

Drive methodology improvements to streamline customer design workflows and enhance verification productivity

Deliver customer-facing technical support with focus on physical verification challenges and solutions

Support customers through complex verification issues and advanced process technology adoption

Ensure maximum customer satisfaction through expert guidance and responsive technical support

Qualification

Advanced CMOS processesLayout verificationParasitic extractionEDA toolsScripting languagesTechnical directionCustomer engagementAnalytical problem-solvingEffective communication

Required

US Citizenship required

Ability to obtain a US Government Security Clearance

Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study

5+ years of experience with advanced CMOS processes (22nm and below)

4+ years of combined experience in layout verification and parasitic extraction EDA tools

4+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting.)

Preferred

Active US Government Security Clearance with a minimum of Secret level

Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study

Hands-on experience in one or more areas ( LVS, DRC,ERC, PERC)

Experience in parasitic extraction tools i.e. StarRC, Quantus, or xACT EDA tools

Experience with major layout editing EDA tools and flows such as ICV, Calibre and Pegasus EDA tools

Rule deck coding experience in ICV, Calibre or Pegasus EDA tools

Experience in providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work

Customer facing experience