NVIDIA · 1 week ago
Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
Santa Clara, CA
Full-time
Onsite
Senior Level
$136K/yr - $218K/yr
5+ years expNVIDIA is widely considered to be one of the technology world’s most desirable employers. As a member of the CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, collaborating closely with the logic design team on micro-architecture definition and feasibility.
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Responsibilities
As a member of our CPU team, you'll be a liaison between Logic design and Physical design teams responsible for achieving timing, area, performance and power goals of the unit
Help define the architecture for next-generation Nvidia coherent interconnects and system-level caches
Qualification
Required
Master's Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience
5+ years of experience in processor or other related high-performance semiconductor designs
Physical design expertise including hands-on synthesis experience, timing analysis, floor-planning and in-depth knowledge of industry standard physical design tools is required
Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team
Preferred
Physical design expertise in high-frequency interconnect/cache/core design is preferred
Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO
Benefits
Equity
Benefits
Company
NVIDIA
NVIDIA is a computing platform company operating at the intersection of graphics, HPC, and AI.
10001+ employees
H1B Sponsorship
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Funding
Current Stage
Public CompanyTotal Funding
$4.09BKey Investors
ARPA-EARK Investment ManagementSoftBank Vision Fund
2023-05-09Grant· $5M
2022-08-09Post Ipo Equity· $65M
2021-02-18Post Ipo Equity
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Jensen Huang
Founder and CEO
Michael Kagan
Chief Technology Officer
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