Apply on Employer Site

Xcelerium · 2 days ago

Senior VLSI Physical Design Engineer

Irvine, CA

Full-time

Onsite

Senior Level, Lead/Staff

10+ years exp

Xcelerium is a fabless semiconductor company developing advanced edge processors that bring AI processing to high-bandwidth sensors and wireless devices. They are seeking a highly skilled Senior SoC/ASIC Physical Design Engineer to lead and drive physical design activities, collaborating closely with RTL and other engineering teams to optimize design performance and efficiency.

Communication HardwareInternetManufacturingSemiconductor

Responsibilities

Develop and Implement PD Flow: Establish a modern physical design (PD) flow utilizing the latest EDA tool fusion and machine learning (ML) techniques to maximize PPA efficiency, optimize resource allocation, and achieve industry-leading time-to-closure and tapeout

End-to-End Physical Design Execution: Perform partition synthesis and physical implementation, including synthesis, floorplanning, power/ground grid generation, place & route, timing, noise, physical verification, electromigration, voltage drop, and signoff checks

Methodology and Automation: Create and refine physical design methodologies and automation scripts to streamline implementation and signoff processes

Cross-Functional Collaboration: Work closely with RTL, DFT, and ASIC design teams to define architectural feasibility, establish timing, power, and area targets, and explore design trade-offs

Drive Design Closure: Utilize an objective, metrics-driven approach to resolve design, timing, and flow issues and ensure predictability in achieving project milestones

Signoff Ownership: Lead signoff closure activities, including static timing analysis (STA), noise analysis, logic equivalency, physical verification, and power integrity (EM/IR)

Qualification

ASIC/SoC physical designRTL-to-GDSII flowsSynopsys EDA toolsPhysical design methodologiesFinFET technologyScripting languagesDesign parameter analysisTeam collaboration

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (Master's preferred)

10+ years of experience in ASIC/SoC physical design and flow development

Expertise in RTL-to-GDSII physical design and signoff flows

Strong experience with Synopsys EDA tools, understanding tool capabilities and underlying algorithms

Proficient in physical design methodologies: synthesis, place & route, STA, formal verification, CDC, and power analysis

Knowledge of FinFET and deep sub-micron CMOS technologies, including power dissipation, leakage, and dynamic behavior

Familiarity with DFT, Scan, MBIST, and LBIST methodologies and their impact on physical design

Proficient in scripting languages (Python, Tcl, Perl, bash/csh) and automation using Makefiles

Skilled in extraction and analysis of design parameters, QOR metrics, and implementing voltage scaling (SVS, DVFS) and SRAM split rail architectures

Proven ability to work collaboratively in dynamic environments, lead design closure activities, and drive execution with a proactive, solution-oriented mindset