Design Verification Engineer jobs in United States
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Meta · 5 hours ago

Design Verification Engineer

positionRedmond, WA
timeFull-time
remoteOnsite
seniorityEntry, Mid Level
money$114K/yr - $172K/yr
date2+ years exp

Meta builds technologies that help people connect, find communities, and grow businesses. The Design Verification Engineer will define and implement verification plans, develop functional tests, and collaborate with cross-functional teams to ensure the highest design quality for Meta's wearable technologies.

Computer Software
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Comp. & Benefits

Responsibilities

Define and implement verification plans, and build test benches for block, IP, sub-system, and SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
Debug, root-cause and resolve functional failures in the design, partnering with the Design team

Qualification

SystemVerilog/UVMC/C++ verificationBlock/IP/SoC verificationEDA toolsPython scriptingGitDebuggingCollaborationProblem-solving

Required

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification
2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Preferred

Experience with revision control systems like Mercurial(Hg), Git or SVN
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch
Experience verifying ARM/RISC-V based sub-systems and SoCs
Experience verifying CPU/GPU designs
Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation
Track record of 'first-pass success' in Application-Specific Integrated Circuit (ASIC) development cycle

Benefits

Bonus
Equity
Benefits

Company

Meta

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Meta's mission is to build the future of human connection and the technology that makes it possible.
dateFounded in 2004
location
Menlo Park, CA, US
people-size10001+ employees
web-link
https://www.metacareers.com/

Funding

Current Stage
Late Stage

Leadership Team

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Kathryn Glickman
Director, CEO Communications
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Christine Lu
CTO Business Engineering NA
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