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Draper · 9 hours ago

Principal Analog Mixed Signal ASIC Layout Engineer

Cambridge, MA

Full-time

Onsite

Senior Level, Lead/Staff

$95K/yr - $245K/yr

7+ years exp

Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA, seeking a talented and motivated individual to join their analog mixed signal ASIC team. The role involves creating complex analog layouts for ASICs used in national security, biomedical, and space applications, while also leading and mentoring other layout engineers.

Defense & Space

Growth Opportunities

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Design and simulate circuits at transistor-level to implement architecture and requirement specifications

Contribute to system-level design

Optimize hardware designs for performance, power, and cost

Evaluate the hardware feasibility of complex algorithms and requirements

Independently contribute to complex chip architectures and designs

Independently drive solutions to complex problems - develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements

Contribute to business development and proposal activities

Develop, document, and teach best practices to less experienced engineers

Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics, contribute to design-for-test development

Perform other duties as assigned

Qualification

Integrated circuit designAnalog layout designCadence VirtuosoCMOS advanced nodesLow power circuit designRadiation-hardened electronicsPhysical verification toolsAnalytical skillsCommunication skillsOrganizational skillsTime management skillsMentor

Required

Requires a bachelor's degree in Engineering, or related field

Requires 7-10 years of experience with a bachelor's degree, or 5-10 years of experience with a master's degree in ASIC Hardware Engineering or related

Proficiency in integrated circuit design

Understanding of integrated circuits, semiconductors, and general computer architecture

Ability to write detailed design specifications

Ability to lead multi-disciplinary technical teams

Excellent verbal and written communication skills

Excellent mathematical skills

Excellent organizational skills and attention to detail

Excellent time management skills with the proven ability to meet deadlines

Strong analytical and problem-solving skills

Ability to prioritize tasks

Demonstrate strong organization, planning, and time management skills to achieve program goals

Preferred

Masters degree preferred

Experience with low power circuit design

Experience with CMOS advanced nodes below 32nm

Experience with radiation-hardened electronics

Experience with Cadence Virtuoso and Siemens Calibre tools

High proficiency in implementing analog designs into full custom layout. PLLs, DACs/ADCs, high speed SerDes, bandgaps, ESD/IO, and more

Ability to recognize layouts vulnerable to failure and ways to fix. ESD/LU, DFM, etc

Fluent in layout effects and how circuit performance can be affected. NW proximity, length-of-diffusion, implant shadowing, EM/IR, self-heating, coupling capacitance, matching techniques, etc

Significant experience with understanding and debugging DRC, LVS, PM, and other physical verification tools and methodologies

Ability to be the sole layout resource for an entire chip, from transistor level layout to chip level integration and tape out

Experience with chip level/top down floor planning and delegating work other layout resources

Ability to communicate technical information across different disciplines and experience levels

Preferred experience with automated tools (Cadence ModGen/autorouter/EAD, Innovus, etc), and methods for transferring data between domains (abstract/LEF)

Understanding of how revision control software operates (SOS, git, SVN, etc)

Able to motivate themselves and operate independently

Ability to mentor others and willingness to be mentored

Experience operating in a Linux environment. Preferred experience with scripting (SKILL, SVRF, tcl)

Experience with FinFET processes, 22nm to 7nm and below

High preference for experience with GAAFET processes and/or photonics processes

Benefits

Workplace flexibility

Employee clubs ranging from photography to yoga

Health and finance workshops

Off site social events

Discounts to local museums and cultural activities

Company

Draper

Glassdoor4.1

We Engineer Solutions for the Nation’s Toughest Problems As an independent nonprofit engineering innovation company, Draper provides engineering services directly to government, industry, and academia.

Founded in 1938

Cambridge, MA, US

1001-5000 employees