Broadcom · 2 hours ago
Analog/Mixed Signal Verilog Modeling Design Engineer
USA-CA Irvine Alton Parkway Bldg 1
Full-time
Onsite
Senior Level, Lead/Staff
$120K/yr - $192K/yr
8+ years expBroadcom is a leading technology company, and they are seeking an Analog/Mixed Signal Verilog Modeling Design Engineer. The role involves developing Digital-Mixed Signal models of analog IPs, interfacing with design teams, and ensuring effective chip verification through advanced modeling techniques.
MobileSemiconductorWireless
Responsibilities
Responsible for developing Digital-Mixed Signal (DMS) models of analog IPs such as touch controller AFEs, wireless power charging, health sensing AFE and satellite AFEs using SystemVerilog language
Interface with analog design team and chip DV team to develop and support analog/mixed signal models for chip verification
Understand Verilog-AMS modeling language
Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package)
Familiar with analog circuits such as LDOs, TIAs, analog muxing, SARADC sample-and-hold (S/H), comparators, DAC voltage converter, buffering and amplification, etc
Understand good coding of RTL of digital design (eg clock divider, decoder, FSM, etc) and testbench creation
Fully familiar with how to run SV .vs. schematic verification for a given leaf SV model
Familiar with Cadence linting & simulation tools (ncsim, xrun, vcs) and analog schematic editor
Hands-on skills in scripting languages (TCL/Perl/Python)
Experience with using AI tools such as Cursor, chipAgents to generate analog SV models and testbench based on a given design spec
Qualification
Required
Responsible for developing Digital-Mixed Signal (DMS) models of analog IPs such as touch controller AFEs, wireless power charging, health sensing AFE and satellite AFEs using SystemVerilog language
Interface with analog design team and chip DV team to develop and support analog/mixed signal models for chip verification
Understand Verilog-AMS modeling language
Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package)
Familiar with analog circuits such as LDOs, TIAs, analog muxing, SARADC sample-and-hold (S/H), comparators, DAC voltage converter, buffering and amplification, etc
Understand good coding of RTL of digital design (eg clock divider, decoder, FSM, etc) and testbench creation
Fully familiar with how to run SV .vs. schematic verification for a given leaf SV model
Familiar with Cadence linting & simulation tools (ncsim, xrun, vcs) and analog schematic editor
Hands-on skills in scripting languages (TCL/Perl/Python)
Experience with using AI tools such as Cursor, chipAgents to generate analog SV models and testbench based on a given design spec
Experience : Bachelor's and 8+ years of related experience
Benefits
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time
Company
Broadcom
Broadcom is a designer, developer, and global supplier of a broad range of analog and digital semiconductor connectivity solutions.
10001+ employees
H1B Sponsorship
Broadcom has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (92)
2024 (77)
2023 (79)
2022 (112)
2021 (110)
2020 (89)
Funding
Current Stage
Public CompanyTotal Funding
unknown2017-10-31Post Ipo Equity
2015-05-28Acquired
1998-04-17IPO
Leadership Team
Greg Singh
CTO for APJ, Enterprise Security Group
Kirsten Spears
CFO and CAO, Broadcom
Recent News
2026-01-11
Company data provided by crunchbase