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Northrop Grumman · 21 hours ago

Sr Principal Engineer Digital

Plymouth, MN

Full-time

Onsite

Senior Level, Lead/Staff

$149K/yr - $224K/yr

6+ years exp

Northrop Grumman is a leader in technological advancements with a storied history in defense systems. They are seeking a Senior Principal Engineer to lead the firmware strategy for defense programs, focusing on FPGA firmware design and integration while mentoring a cross-functional team of engineers.

AerospaceData IntegrationManufacturingRemote SensingSecurity

Growth Opportunities

No H1B

Security Clearance Required

U.S. Citizen Only

Responsibilities

Define and maintain the FPGA firmware architecture for assigned programs, ensuring scalability, reliability, and compliance with system level requirements

Lead the Firmware IPT, coordinating with hardware, software, systems, test, and program management to deliver projects on schedule and within budget

Develop complex firmware blocks in VHDL (preferred) or Verilog targeting various FPGA families such as Intel Agilex, Arria 10, Max 10, and Xilinx

Create and execute verification plans using simulation, hardware in the loop, and on board debugging tools (e.g., ModelSim, Vivado, Quartus)

Manage design constraints (timing, power, I/O) and perform static timing analysis to meet critical performance targets

Integrate firmware with hardware/software, including bus protocols (I²C, SPI, UART, RS 232/422/485, JESD204B, CSI/MIPI, Ethernet) and custom IP blocks

Lead technical documentation efforts (architecture documents, interface control documents, test plans, release notes) and ensure configuration management compliance

Mentor junior engineers, conduct design reviews, and drive continuous improvement initiatives (Six Sigma, DFA/DFM)

Provide risk management and mitigation strategies for firmware related technical risks

Interface with customers and senior leadership to translate stakeholder requirements into effective firmware solutions

Qualification

FPGA DesignVHDLFirmware IntegrationSimulation ToolsTechnical DocumentationTeam CollaborationDSP FirmwareProcess ImprovementLeadership Experience

Required

Education: B.S. in Electrical or Computer Engineering with 8+ years relevant experience OR M.S. with 6+ years

FPGA Design: Proven experience in designing complex FPGA firmware using VHDL or Verilog

Verification: Proficiency with simulation tools (ModelSim, Vivado, Quartus) and hardware debugging tools (logic analyzers, oscilloscopes)

Timing Closure: Expertise in managing design constraints to meet stringent timing and performance targets

Integration: Experience with hardware/software integration for embedded systems and soft processor interfacing

Documentation: Demonstrated ability to produce comprehensive technical documentation

Team Collaboration: Excellent interpersonal skills for effective cross functional teamwork

Security Clearance: U.S. citizenship; ability to obtain and maintain a DoD Secret clearance (active preferred)

Preferred

Bus Protocol Expertise: Experience with protocols such as I²C, SPI, RS232, JESD204B, and CSI/MIPI

Preferred HDL: Strong preference for VHDL, with Verilog experience considered beneficial

DSP Firmware: Demonstrated experience with digital signal processing functions (lowpass, bandpass, highpass filters, comb filters, Hilbert transforms, PLLs, etc.)

Device Families: Familiarity with Intel Agilex, Arria 10, Max 10, as well as Xilinx UltraScale+ devices

Toolset Proficiency: Experience with tools such as Vivado, Model Composer, Synplicity, MATLAB/Simulink, Altera DSP Builder, and HDL Code generators

IP Creation & Integration: Proven ability to develop reusable IP blocks and integrate thirdparty IP

Full Product Lifecycle: Involvement from concept through production test and field support

Military Test Experience: Knowledge of testing requirements specific to military electronics (extreme temperature, vibration, EMC)

Process Improvement: Familiarity with SixSigma methodologies and design for assembly/manufacturability (DFA/DFM) principles

Leadership Experience: Prior success leading an IPT or firmware development team in a highstakes defense environment

Active DoD Clearance: An active DoD Secret clearance is a plus