Arm · 4 days ago
Principal Fuse/JTAG Design Lead
Chandler, AZ
Full-time
Hybrid
Lead/Staff
$241K/yr - $326K/yr
15+ years expArm is a leading technology company focused on developing SoCs for various application segments. They are seeking a Principal Fuse/JTAG Design Lead to lead the team responsible for the development of the JTAG and Fuse Subsystems, ensuring high-quality design specifications and effective collaboration with partner teams.
AnalyticsElectronicsInternet of ThingsSemiconductorSoftware
Responsibilities
As a lead design engineer with a knowledge of subsystems and SoCs you will be leading an IP development team which owns our reconfigurable Fuse and JTAG Subsystems
Work with the Architect(s) to understand Subsystem requirements, and develop the design specifications which meet the quality, reliability, manufacturing and reconfigurable needs across multiple SoC's
Your key technical responsibilities will include crafting design micro-architecture specifications, developing the RTL, fixing bugs, running design checks and contributing to the generation of implementation constraints
Your key leadership responsibilities will include technical guidance and mentorship of the design team, engaging with partner teams for collaborative improvements in tools, technologies, methodologies, and capabilities
Partner with the verification lead to review test plans and help debug design issues in addition to crafting UVM components for IP and SoC integration of the Subsystems
As lead of the design team, you will drive unification and efficient methods, as well as drive new methodologies used by the team
Act as 1-Arm ensuring the best solutions are what Arm uses
Required to work with Project Management to define plans and execute schedules flawlessly
Qualification
Required
Bachelors or Master's Degree in Computer Science or Electrical/Computer Engineering or a similar related field
15+ Years' Experience Working In Design Of Complex Subsystems Or SoCs
Experience in digital hardware design for complex systems using System Verilog
Experience with working with analog hard IP integration, timing diagrams, BMODs
Experience with reconfigurable IP / Subsystem design
Experience with power and clock domain crossing
Experience with static design checks like linting, CDC/RDC, X-propagation
Experience with all stages of design: initial concept, specification, implementation, testing, documentation and support
Experience collaborating with the verification team on design quality closure
Experience with Perl, Python or other scripting language
Leadership, mentoring or coaching experience
Preferred
Experience with ARM-based designs and/or ARM System Architectures
Experience developing designs for OTP/Fuse usage models and JTAG/TAP protocols
Experience with SoC system use cases and debug methodologies
Experience developing and integrating subsystems for PCIe, UCIe, DDR/LPDDR/HBM, Ethernet etc
Experience with DFT use cases and methodologies: RTL testability, scan insertion, OCC
Company
Arm
Arm’s foundational technology is defining the future of computing. A future built by the greatest technology ecosystem in the world.
5001-10000 employees
H1B Sponsorship
Arm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (295)
2024 (166)
2023 (164)
2022 (123)
2021 (103)
2020 (133)
Funding
Current Stage
Public CompanyTotal Funding
unknown2016-07-18Acquired
1999-01-15IPO
Leadership Team
Rene Haas
CEO
Jason Child
EVP & CFO
Recent News
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