Qualcomm · 4 hours ago
High-speed Interface Micro Architect and RTL Design Engineer
San Diego, CA
Full-time
Onsite
Senior Level
$164K/yr - $246K/yr
5+ years expQualcomm Technologies, Inc. is seeking skilled digital design engineers to contribute to the development of next-generation, high-performance, low-power interface IPs. The role involves collaborating with a cross-functional team to architect, design, implement, and validate complex IP blocks, supporting multiple business units within Qualcomm's product portfolio.
Artificial Intelligence (AI)Generative AISoftwareTelecommunicationsWireless
Responsibilities
Architect and define the digital design of high-speed interface IPs (e.g., SerDes, DDR, die-to-die) in close collaboration with system architecture and analog teams
Develop micro-architecture and implement RTL for complex mixed-signal IP blocks
Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area (PPA)
Utilize industry-standard ASIC design tools for lint checking, clock domain crossing (CDC) analysis, design-for-test (DFT), synthesis, formal verification (FV), and static timing analysis (STA)
Design and analyze DFT logic, including ATPG for stuck-at fault (SAF) and transition delay fault (TDF) coverage
Create comprehensive design documentation, including hardware specifications
Collaborate with the design verification (DV) team to define test plan, verify the design, and fix bugs
Work with the physical design (PD) team to support floor planning, placement, and timing closure of IPs
Support SoC integration and debug, including pre-silicon simulation and post-silicon bring-up
Qualification
Required
Master's degree in Electrical Engineering, Computer Engineering, or a related field
7+ years of experience in RTL and ASIC design
5+ years of hands-on experience in micro-architecture and digital design for mixed-signal IPs such as SerDes (PCIe, USB, UFS, MIPI), DDR PHY, PLLs, DACs, ADCs, and sensors
Proficiency with industry-standard front-end ASIC design tools including VCS, Fusion Compiler, PrimeTime, Power Compiler (PTPX), DFT Compiler, Spyglass, and others
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience
Preferred
Ph.D. in Electrical Engineering with 5+ years of industry experience in high-speed digital circuit design
Strong background in low-power digital design techniques
Expertise in computer architecture, digital signal processing, and algorithm development
Experience developing automation scripts and design productivity tools using Python or Perl
Benefits
Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
10001+ employees
H1B Sponsorship
Qualcomm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2013)
2024 (1910)
2023 (3216)
2022 (2885)
2021 (2104)
2020 (1181)
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
Leadership Team
Cristiano Amon
President & CEO
I
Isaac Eteminan
CEO
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