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Teradyne · 1 day ago

Senior Logic Design Manager (Teradyne, North Reading)

North Reading, MA

Full-time

Onsite

Senior Level, Lead/Staff

$200K/yr - $320K/yr

10+ years exp

Teradyne is a global leader in test and automation solutions, ensuring electronic devices work correctly through innovative technology. They are seeking a Senior Logic Design Manager to lead FPGA development projects, manage a team, and collaborate with engineering teams to deliver high-quality semiconductor test instruments.

Consumer ElectronicsIndustrialIndustrial Automation

No H1B

Hiring Manager

Kyle Dunbar

Responsibilities

Manage multiple simultaneous (typically 2-3) FPGA development projects including: Project planning, Schedule/budget tracking, Resource management including contractors on and offshore, Status reporting to management, Technical oversight: doc/code reviews, bug tracking

Line management of a ~4-6 member team

Help maintain/improve FPGA development process/tools

Hands-on FPGA architecture, implementation, testing and product integration debug as required

Collaborate with Hardware, Software and Systems engineering to develop high quality semiconductor test instruments

Qualification

FPGA design experienceFPGA project managementRTL coding (Verilog)Digital simulation toolsStatic timing analysisDigital design quality toolsBug tracking toolsSource control systemsProject scheduling toolsHigh level programming CHigh level programming C++Embedded processors experienceDigital signal processingHardware for automated test equipmentCommunication skills

Required

Minimum of 10 years of FPGA/ASIC design experience

Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects from concept, architecture exploration, design implementation, lab validation to production release

3-5 years of experience as a first level manager of an engineering team

Extensive experience coding RTL (Verilog preferred)

Extensive experience using digital simulation tools (Cadence preferred)

Extensive experience using static timing analysis tools

Experience designing with the following: PCIe, DDR3/4, AXI, ethernet, SPI, SERDES

Experience using digital design quality tools e.g. LINT, CDC, LEC

Experience with either AMD or Altera FPGAs and development tools, preferably both

Experience with bug tracking tools (Jira etc.)

Experience with source control systems (Clearcase, Git, CVS) and continuous integration

Familiarity with digital verification tools and methodologies (preferably UVM)

Experience with project scheduling tools (e.g. Microsoft project)

Excellent presentation and communication skills

BS required, advanced degree preferred in electrical engineering, computer engineering, computer science or related technical field from a top university or engineering institution