NVIDIA · 2 days ago
Senior Timing Engineer - Circuits
US, CA, Santa Clara
Full-time
Hybrid
Senior Level
$168K/yr - $264K/yr
6+ years expNVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. They are seeking a motivated Senior Timing Engineer (Circuits) to join their dynamic Circuit Solutions Group, focusing on improving design and timing quality while solving complex technical challenges through collaboration.
AI InfrastructureArtificial Intelligence (AI)Consumer ElectronicsFoundational AIGPUHardwareSoftwareVirtual Reality
Responsibilities
Participate in groundbreaking processor design in deep submicron technologies
Work as part of a global circuits team alongside circuit designers to drive timing analysis and signoff of custom circuit macros (digital, semi-custom and analog mixed-signal)
Apply knowledge and experience to standardize improving timing convergence flows while working with methodology teams
Develop timing models and methodology for innovative and unique custom macro designs
Validate timing of custom circuit designs using STA tools including PrimeTime, Tempus and various SPICE simulation tools
Work with circuit designers, tool developers, and timing methodology teams to validate macro level timing accuracy and correctness
Work with PD, DFX, Clocks, and other teams on timing signoff strategy, timing constraints, timing and power convergence, DFT, as well as timing ECO implementation
Qualification
Required
BS (or equivalent experience) in Electrical or Computer Engineering
6+ years of experience for Masters and 8+ years for Bachelors with majority of experience in custom circuit timing analysis/signoff
Expertise and in-depth knowledge of industry standard STA tools such as Primetime, Tempus, and other timing analysis tools
Proven experience in timing constraints generation and management
Basic level understanding of transistor-level circuits and SPICE simulations for correlating to STA and noise results
Expertise in analysis and fixing of timing paths through ECOs including crosstalk and glitch noise
Knowledge in process variation effect modeling and experience in design convergence in multi GHz deep submicron technology
Familiarity with clocking specs such as jitter, IR drop, skew, crosstalk, etc
Solid understanding of extracted timing models and the usage of .libs in Primetime
Great teammate with outstanding interpersonal skills
Preferred
Understanding of DFT logic and experience with DFT timing signoff for various modes e.g., shift, capture, BIST, etc
Knowledge of timing closure strategies for digital logic/macros part of AMS designs/IPs
Experience in critical path planning and crafting
Experience in methodology and/or flow development as well as automation
Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes as well as strong scripting skills for flow automation; experience with TCL, Python is a plus
Benefits
Equity
Benefits
Company
NVIDIA
NVIDIA is a computing platform company operating at the intersection of graphics, HPC, and AI.
10001+ employees
H1B Sponsorship
NVIDIA has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
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Funding
Current Stage
Public CompanyTotal Funding
$4.09BKey Investors
ARPA-EARK Investment ManagementSoftBank Vision Fund
2023-05-09Grant· $5M
2022-08-09Post Ipo Equity· $65M
2021-02-18Post Ipo Equity
Leadership Team
Jensen Huang
Founder and CEO
Michael Kagan
Chief Technology Officer
Recent News
2026-01-16
2026-01-16
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