KP Construx · 10 hours ago
Physical Design Lead
United States
Full-time
Remote
Lead/Staff
10+ years expKP Construx is seeking a Physical Design Lead to oversee all physical design activities from RTL handoff to final GDSII delivery. The role involves defining execution strategies, collaborating with various teams, and providing technical leadership to ensure high-quality design implementation.
Oil & Energy
Responsibilities
Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery
Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow
Architect and execute floorplanning strategies for large, hierarchical SoCs, including:
IP integration and macro placement
Physical partitioning and hierarchy definition
Power grid architecture and clock distribution topology
DIE size, aspect ratio, and physical constraints
Collaborate with Architecture and RTL teams to ensure physical feasibility, timing closure readiness, and area/power targets
Lead block-level and top-level PnR using industry standard EDA tools (Cadence, Synopsys)
Drive timing convergence across corners, modes, voltage domains, and operating conditions
Own optimization for PPA (Power, Performance, Area), congestion mitigation, and physical integrity
Implement CTS and drive skew, latency, and clock power optimization
Lead IR/EM sign-off strategy, thermal analysis, and full chip physical verification (DRC/LVS/ERC)
Integrate and validate low power methodologies, including UPF/CPF flows
Partner with DFT and PD teams to ensure scan insertion, BIST structures, and test modes are physically robust and timing clean
Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing
Set physical design quality standards, conduct design reviews, and ensure flawless execution through tapeout
Provide technical leadership to a team of junior and mid-level physical designers
Mentor, coach, and guide engineers in methodology, debug, and best practices
Champion continuous improvement across flows, scripts, and design methodology
Qualification
Required
BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field
10+ years of relevant experience in ASIC Physical Design
Deep expertise in: Floorplanning, Place & Route, CTS, STA/Timing Closure, Physical verification & sign-off, Power integrity (IR drop/EM), Low power design and UPF
Strong hands on proficiency with Cadence and/or Synopsys physical design toolchains
Solid understanding of RTL-to-GDS flows, design architecture trade-offs, and SoC integration complexities
Ability to translate product requirements into physical design goals, budgets, constraints, and deliverable plans
Preferred
multiple tape-outs at advanced technology nodes (16nm → 3nm preferred)
Company
KP Construx
0-1 employeesFunding
Current Stage
Early StageCompany data provided by crunchbase